Rorschach Testing 273 Engineers With The Verilog-VHDL Contest
John Cooley
[ Editor's Note: At the Boston VIUF and at the recent Japanese Synopsys
Users Group meeting, I had quite a few non-Americans ask me for the
write-up of the reader's response to the "You Be The Judge" article
on the Verilog/VHDL design contest. In addition, quite a few American
engineering academics have asked for the same. (Although it appeared
in the Sept. issue of "Integrated System Design" none of these groups
could get a copy because this magazine only targets the American
engineering design community.) Because most Americans are thinking
about Thanksgiving this week, I felt this would be a good time to put
this final write-up on the Internet for the non-Americans. - John ]
!!! "It's not a BUG, jco...@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / RORSCHACH TESTING 273 ENGINEERS
_] [_ WITH THE VERILOG/VHDL CONTEST
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
In March '95, at the annual Synopsys Users Group meeting, a 90 minute ASIC
design contest was held. Using either Verilog or VHDL the 14 contestants
were to create a gate netlist for the fastest fully synchronous loadable
9-bit increment-by-3 decrement-by-5 up/down counter that generated even
parity, carry and borrow.
Of the 9 Verilog designers in the contest, only 1 didn't get to a final gate
level netlist because he tried to code a look-ahead parity generator. Of the
8 remaining, 3 had netlists that missed on functional test vectors leaving 5
Verilog designers who got fully functional gate-level designs. The surprize
was that, during the same time, *none* of 5 VHDL designers in the contest
managed to produce any gate level designs.
In the July issue of "Integrated System Design", I published a very detailed
write-up of the contest. As a sort of industry-wide Rorschach test, I asked
the readers to e-mail me their background, their vote for whether Verilog or
VHDL "won", and the open-ended question of why they thought the way they did.
Here's what 273 ASIC design engineers were thinking...
DEMOGRAPHICS 88 VHDL-only, 76 Verilog-only, 66 bilinguals, and 43 unknown
language users replied. None of the following people's opinions were
tabulated: 19 asking only for the contest's test suites, 17 people employed
by EDA vendors, 3 university CS types, a chemistry professor, an EE PhD
candidate seeking permission to translate the design contest into Estonian,
3 EDA sales pitches and one "Christ is Coming Soon!" letter. Four ESDA
vendors wrote for the contest specs making great claims in the process but
were never heard from again after getting them.
PAYBACK TIME Because of all the time and energy some the EDA sales staffs
put into pushing VHDL onto engineers happy with Verilog, this contest seemed
to be a clarion call for Verilog customers (14 to be exact) to tell me the
shenannigans they suffered at the hands of these EDA vendors. Synopsys, Inc.
topped the perpetrator list because they had a Verilog/VHDL synthesis tool
but only a VHDL simulator (VSS) to go with it. Hence, their sales staff was
quite motivated to creatively work overtime promoting VHDL over Verilog.
> When I worked at HP Roseville, I remember taking my first Synopsys training
> class. The instructor from Synopsys kept telling us that we were making a
> grave mistake using Verilog and that EVERYONE who was anyone was using
> VHDL. (I actually was worried at the time we had chosen the wrong
> language, and that he was really unbiased. As I look back it is obvious
> that he was probably a VSS VHDL salesman and did Design Compiler training
> on the side.) I'm glad we chose Verilog, especially when teaching new
> engineers and when getting our SW/FW folks (who eat/sleep/breathe "C") to
> understand the HDL I have written. I would really encourage any new HDL
> designer to choose Verilog rather than VHDL, since it is much easier to
> learn, use and eventually master.
>
> - Scott C. Petler
> Next Level Communications, Inc.
I laughed out loud when I saw this next letter. At the Synopsys Users Group
meeting three years ago, the HP Boise Laserjet VHDL "success" story was a
main event. And recently, Synopsys even used it in a major ad campaign
promoting VHDL with synthesis in all the trade journals!
> I have spent most of my design life (last 4 years) working on VHDL designs.
> Recently, I have been forced into the Verilog camp by a vendor. My initial
> concerns that Verilog would not have the functionality that I needed have
> been proven wrong. Verilog does what I need better - and the simulators
> are faster than VHDL simulators.
>
> Since VHDL was driven mostly by the government which has no interest in the
> productivity of the designers, it is not surprising to see your results
> from the contest. VHDL syntax hinders progress and does not improve the
> robustness or quality of the design. The behavioral compilers, not VHDL,
> make the most sense for doing even more sophisticated design work.
>
> Please don't make be go back to VHDL!
>
> - Robert Rust
> Hewlett Packard Boise Printer Division
HOW TO NOT LIE WITH STATISTICS To my surprize, hardly anyone (2 VHDL-only
users) tried to say this was statistically insignificant, but 4 (5%) VHDL-
only, 5 (7%) Verilog-only, 3 (5%) bilinguals, 3 (18%) EDA vendors, and one
(25%) professor thought is was mathematically kosher.
> One question that you have the VHDL bigots make in this "trial" can be
> completely refuted: the results are statistically significant as the term
> is usually defined. To say a result is statistically significant, you
> show that it was very unlikely to be achieved by chance. Given: 9 Verilog
> designers and 5 VHDL designers, choose 8 winners at random. What is the
> chance that they will all be Verilog designers?
>
> Answer: (9/14)*(8/13)*(7/12)*(6/11)*(5/10)*(4/9)*(3/8)*(2/7)
> = 0.002997
> = 1/333.7
>
> So there is one chance in 333.7 that this result is purely by chance. We
> can't argue that this result isn't statistically significant given this
> figure. This is a greater than 99% confidence level. If we take one VHDL
> designer out (the one who suffered from the VHDL simulator bug), we get
> (9*8*...2)/(13*12*...6) or 1/143.
FROM THE FOUNDRY Rather than risk losing any business or possibly angering
customers, six ASIC foundry and three FPGA vendors wrote carefully balanced
replies that said effectively: "Whatever the customer wants is right." One
former foundry person wrote on condition of anonimity:
> In a previous life, I worked as an onsite applications engineer for an ASIC
> vendor. The customer that I supported was developing 17 ASIC's for a large
> program. The customer chose to develop some of the designs in VHDL and
> others in Verilog. All were synthesized using Synopsys. The smallest
> design was 15K gates, the largest was 100K gates. I interviewed the design
> teams to gather some interesting statistics. Conclusions were:
>
> 1) Designs done in Verilog were, without fail, completed faster than
> those done in VHDL. (In terms of gates/manweek.)
>
> 2) Adding designers to VHDL and Verilog based designs SLOWED the
> gates/manweek metric, but adding designers to VHDL-based designs
> had a greater negative impact. (Probably due to data-typing issues.)
>
> 3) Single or dual-person design teams out performed all others.
>
> The designers (80) were of various experience levels, working in groups of
> 2 to 10. From end of specification to final signoff, the highest
> performancing was a Verilog team at 1500 gates/manweek, the lowest was a
> VHDL team with 8 gates/manweek!
VHDL'S STRATEGIC RETREAT In the engineering press and on the Internet prior
to the Verilog/VHDL Design Contest, the VHDL bigots managed to create an
image that the only problem their language of choice had was in convincing
the ASIC foundries to provide VHDL libraries. Hence, the big media presence
of "VHDL Initiative Towards ASIC Libraries" (VITAL). With the Design Contest
results 39 (44%) VHDL-only, 4 (5%) Verilog-only, 19 (29%) bilinguals, and 14
(33%) unknown language users conceded that Verilog "wins" in low level gate
type designing, but VHDL "wins" in higher level abstract designing. That is,
VHDL is retreating from gate level design to "own" high level design. (Just
weeks before the Design Contest, VHDL proponents were openly claiming VHDL
was just as good at gate level ASIC design as Verilog was.)
> I've successfully used both languages, think that the results of the
> contest are directly correlated to the structure of the languages. It
> exactly mirror my experiences. Given this, I still prefer VHDL. My first
> design was with Verilog and on the first day (after I'd taken the Synopsys
> Verilog class) I was able to write useable code that was simulatable and
> synthesizable. I found the language relatively simple and easy to use, and
> thus easy to produce results with. When I changed jobs I started using
> VHDL and have produced several large chips with it. It took me more than a
> week to get my first VHDL code to compile, not to mention simulate. At
> first I couldn't stand VHDL, but as time went by I found that it's more
> structured, verbose and abstract from actual hardware. Although harder
> to learn and easier to mess up, it's valuable on large projects.
>
> - Sean Atsatt
> Seagate
TESTING MORE IMPORTANT For some engineers testing was more important than
other issues: 14 (16%) VHDL-only and 9 (12%) Verilog-only stated that their
chosen HDL was best for this; 9 (14%) bilinguals and 4 (9%) unknowns liked
VHDL on testing; 8 (12%) bilinguals and 1 unknown preferred Verilog.
> It's clear from the contest that Verilog can get you to a netlist faster
> than VHDL - period end of story. BUT my experience has shown that the
> amount of time to generate a netlist is small in comparison to the over
> all ASIC design schedule. Verification (i.e. test bench generation) makes
> up most of the ASIC design schedules I put together. Verilog's C-like
> structure provides a very flexiable environment which integrates very
> smoothly into most test bench solutions. In addition, focusing on test
> benchs illuminates one of Verilog's best features: the PLI. I don't
> believe VHDL provides a PLI counterpart. Without a PLI many of the
> third part tools that I rely on, such as Signalscan, would not be available.
> At GI we have made use of Verilog's PLI for many tasks ranging from memory
> efficient input stimulus handling to automated test vector generation.
>
> - Rick Price
> General Instrument Corp
EXPERIENCE QUESTIONS Quite a number of VHDL proponents raised the issue that
the VHDL contestants might not be experienced with the tools they had at hand
or in ASIC design itself. (No one questioned the experience of the Verilog
contestants because all but one got to gates.) The VHDL contestants used
Synopsys for synthesis and had a choice of Cadence and Synopsys for VHDL.
What follows are the sizes of all the ASIC's and FPGA's the VHDL contestants
have designed plus what EDA tools they've used.
TABLE 1) ASIC, FPGA & TOOL EXPERIENCE OF VHDL COMPETITORS
----------------------------------------------------------------------------
Ravi Srinivasan ASIC's: 60K, 115K partial ASIC's: 30K, 45K FPGA's: 0
Texas Instr. Tools: Synopsys VHDL & Design Compiler, Aida, Verilog-XL
Jan DeCalwe ASIC's: 60K, 22K, 65K, 35K, 83K FPGA's 3K, 6K, 4K, 2K
Easics, Ltd. Tools: Synopsys VHDL & Design Compiler, Actel P&R, Altera
MaxPlusII, Verilog-XL
Jeff Solomon ASIC's: 125K (schm.) partial 55K FPGA's: 2K, 6K, 10K
NASA Goddard Tools: Synopsys VHDL & Design Compiler, Concept/Valid,
Cadence LWB RapidSim, LSI CMDE
Prasad Paranjpe ASIC's: 17K, 20K, 50K, 30K partial ASIC's: >5 FPGA's: 0
LSI Logic Tools: Synopsys VHDL & Design Compiler, Vantage, LeapFrog,
Verilog-XL, IKOS, MTI, LSI CMDE
Vikram Shrivastava partial ASIC's: lots of synthesis/static timing/CMDE
LSI Logic Tools: Synopsys VHDL & Design Compiler, Verilog-XL, CMDE
---------------------------------------------------------------------------
The Verilog based contestants had similar tool and ASIC design experiance.
One noteable exception was Howard Landman of HaL Computers. In his 15 years
of CAD management experience Landman has never designed a single ASIC, yet,
using Verilog he managed to take third place in the design competition!
FAIRNESS: Of those 44 (16%) engineers who commented on fairness, 6 (2%)
(all VHDL-only's) felt the contest was "rigged" in Verilog's favor (because
they felt it was too low level) while the remaining 38 (14%) overall
designers saw it as honorable.
> Even before I read the "Closing Arguments to the Jury..." I was thinking
> that this design contest was perfect because it showed exactly what
> engineers are up against - tools are late, support is incomplete and/or
> inexact, workstations crash inexplicably, testing is incomplete, etc. The
> only thing missing was a change in the specification 10 minutes before the
> end of the contest. Cool contest - thanks for all the work.
>
> - Richard Schmidt
> Exabyte
Two engineers felt that Steve Golson should have won because his design met
the design spec while Larry's didn't -- but this error wasn't caught by the
faulty test suite.
> Steve Golson is the winner. Clearly stated in the spec: "11" - Q holds
> state. The inability of your testbench designers to adequately test the
> design should not be held against Steve (or should I say assist Larry).
> The bottom line must be that the design is functionally accurate.
>
> - Michael Fitzsimmons
> Motorola
TYPE WARS: The most controversial topic was whether strong typing is a good
thing or a bad thing. Some VHDL-proponents felt it was VHDL's core strength,
while other VHDL-proponents saw strong typing as an increadable annoyance!
Those who knew VHDL had very strong opinions on this. Of the bilinguals,
19 (29%) hated strong typing, 6 (9%) loved it, 6 (9%) noted it but couldn't
decide. Of the VHDL-onlys, the breakout was 13 (15%) hate, 17 (19%) love,
10 (11%) noted but couldn't decide. Of Verilog-onlys and unknowns, 7 (5%)
hated, 4 (3%) loved, 6 (4%) noted but couldn't decide.
> I thought the contest was a good one and I'm not seriously surprised by the
> results. I think the difference is in the nature of the languages,
> particularly the strong typing of VHDL, which at least one of your entrants
> had trouble with. VHDL forces you to think carefully about datatypes; if
> the design is simple logic, then this is a liability in terms of quick
> design time. VHDL has a better chance of producing a correct design if
> there is a mix of signal types, because you are forced to make sure they
> all convert correctly. C++ versus C is an analogy, the strong class
> binding of C++ objects can make for extra work up front making sure the
> types match up. In the long run, the design is more robust and easier to
> maintain because of it. I'm an IC designer who has used both - I'd use
> either one in real life, but I think verilog has the edge in quick draw
> contests.
>
> - Steve McChrystal
> Siemens Components Inc.
IOWA STATE UNIVERSITY It appears that the Design Contest's results have even
been verified by academia. What I liked about this unintentional validation
is that it's not 90 minutes. That is, there was all sorts of time for the
designers to do what they wanted. (I've recieved over 100 letters total
starting with: "Your results didn't surprize me one bit!" If they were from
the VHDL oriented I got explanations that VHDL tools took longer to run, VHDL
was more verbose, and needed more intial time to get results. If they were
from the Verilog oriented, I got explainations that Verilog was essentially
C with wires, registers, built in flexable HW data types, concurrency and "it
should naturally win.")
> Actually, an interesting look at VHDL vs. Verilog was accidentally done in
> our graduate level logic synthesis course. We recently got Synopsys Design
> Compiler, Synopsys VHDL and Cadence Verilog-XL. While The rest of the
> class did their projects in VHDL, my lab partner and I did ours in Verilog.
> (We learned Verilog on our own; unlike my VHDL classmates, we had no class
> lectures, no T/A help, no professoral help.)
>
> The results of this were overwhelmingly in favor of Verilog as a tool to
> teach HDLs. Our final project, a 7500 gate, 35nsec RISC processor was ~25
> pages of Verilog. The VHDL people all ended up rushing near the end to
> just make something which worked and could be synthesized. Several groups
> failed at this altogether! (Whereas our project grew so large in
> functionality, our only problem was finding a workstation which had enough
> memory to handle the synthesis of the top level design.)
>
> The general comments in talking to the other students was they spent a
> majority of their timing fighting VHDL/Synopsys. We spent a majority of
> our time doing design work, and optimization.
>
> - Jeff Echtenkamp
> Iowa State University
BILINGUAL JUDGEMENTS The opinions I value the most are those of the bi-
linguals because they know both sides of the story. Of the bilinguals, 39
(59%) personally preferred Verilog overall, 16 (24%) were HDL neutral,
6 (9%) personally preferred VHDL, and 5 (8%) didn't comment on this.
> My transition from VHDL to Verilog came about 2 years back when I worked
> on a design which was about 45K gates. I learned Verilog as the ASIC
> Vendor we worked with was only comfortable doing a final signoff in Verilog
> rather than VHDL. With the flavor of both the languages, here are my
> comments:
>
> 1) VHDL is a good structured HIGH level language but I feel Verilog is
> closer to actual hardware which is being designed.
>
> 2) As far as behavioral goes, I rank VHDL at par with Verilog, but when
> it comes to RTL, I consider Verilog has the edge over VHDL as far as
> the time to market ( i.e. meeting the design schedule is concerned.)
>
> As far as the contest goes, I think verilog has again proved the point.
> Yes, with VHDL you can achieve the same target but at the cost of design
> time and support. In the present industry, time to market a product is
> the key to success. If a particular market window is missed, the ASIC and
> the man-months spent on it are a sheer waste. I strongly feel that given
> the choice and the design time I would opt for Verilog.
>
> - Subhodip Ghosh
> Western Digital Corp.
DON'T SHOOT THE MESSENGER! I'd like to close with the observation that this
design contest wasn't designed to be a referendum on Verilog vs. VHDL, but
it accidently became this. I was swamped with e-mail from both the Verilog
*and* VHDL camps *both* saying that Verilog won in this contest. Judging the
contest overall 175 (64%) felt "Verilog won", 16 (6%) felt "VHDL won", 48
(18%) felt "inconclusive" and 36 (13%) never voted! Along party lines, 70
(92%) Verilog-onlys voted "Verilog won" and 39 (44%) VHDL-only's did either
an "inconclusive" or "no vote."
> I am in the defense industry, and therefore we went right to VHDL when we
> switched to designing ASICs using HDLs. I have never learned Verilog. I
> have always thought the extremely tight typing in VHDL caused a lot of
> inefficiencies, and my guess is that this had a major effect in the contest
> results. Your contest seemed very fair to me. I would call Verilog the
> obvious winner.
>
> - Jim Levie
> Northrop Grumman
Yes, quite a few VHDL-only EDA companies like Synopsys, Mentor, Zycad, IKOS,
Model Tech, and ViewLogic have suddenly been working to either buy or
develope Verilog products for their customers. I don't see them leaving the
VHDL business, though. In my own consulting practice I've just finished a
Verilog ASIC for one customer and am now writing VHDL training material for
another. For the next few years I feel being fully Verilog/VHDL bilingual,
just like most EDA companies, is the wave of the future.
- John Cooley
part-time EDA Consumer Advocate
full-time contract ASIC/FPGA designer
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3881 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jco...@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
John Cooley
the U.S. trade pubs (after they've been published) because:
- I've received very positive responses while doing this from engineers
who can't get these pubs yet want the news (namely the Europeans, the
Japanese, the Austrailians, & the academics greatly appreciated it.)
- The Internet lets me explore ideas thoroughly because there's no space
limitation in publishing. (Trade Pubs usually limit article sizes.)
- Most importantly, I know I don't know everything. I want to encourage
my fellow engineers to tell me if I'm right/wrong/somewhere-in-between
and *WHY*. (It helps in future articles -- write me!)
(As always, please indicate what parts of your reply are not publishable
otherwise I default to it being *completely* publishable.) - John ]
!!! "It's not a BUG, jco...@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - /
_] [_ INDUSTRY GADFLY: "The Fall(ing) VIUF '95"
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Sparce Attendance
-----------------
After attending the Fall meeting of the VHDL International Users Forum (VIUF)
last week in Boston, it was painfully obvious that the six year old VIUF was
in trouble. I can now verify the rumors that VIUF was having serious
problems attracting attendees after I personally counted, at the height of
the conference, only 156 people watching the 11:00 AM Exective Panel plus an
additional 23 others I found either milling around in the hallway or setting
up demos in the exhibit room. This count matched similar private reports
that I had heard concerning the last 4 or so VIUF's. (To put it in
perspective, VIUF's linguistic arch-rival, the International Verilog
Conference (IVC) went in three years from 213 attendees in 1992 to a record
510 attendees at this last March's IVC.)
I'd rather not waste your time interpreting why VIUF is hurting but will warn
you that it may not be because the VHDL language itself has failed to catch
on in the U.S. market. That is, it's possible that VIUF may be severely
stunted because it meets every six months while IVC meets just once a year.
(Hopefully this will change with co-locating the two conferences next year.)
Tutorials
---------
Out of the Sunday tutorials, quite a few users gave positive comments on Joe
Pick's (from Synopsys) VHDL coding and VHDL synthesis tutorials. (Because I
teach synthesis as a business, I was more interested in Steve Ives' and Elise
Campbell's [both from Top Down Design] tutorial on memory modeling with VHDL
because some of it was new to me.) A number of engineers commented it was
interesting to see Janick Bergeron's (from Qualis) Verilog/VHDL and
VHDL/Verilog tutorials at an obstensively pro-VHDL conference.
The Papers
----------
From the VIUF proceedings, I was quite interested in a paper presented by
four Raytheon engineers that had actual metrics accompanying a discussion
about enhancing design productivity using i-Logix tools and the mysterious
Synopsys Behavioral Compiler. (The mystery is because users have been
having a hard time getting detailed non-Synopsys opinions on Behavioral
Compiler.)
Manual RTL Approach Behavioral Compiler Approach
--------------------- ----------------------------
Design Methodology RTL VHDL Top-Down Behavioral Top-Down
Lines of VHDL 23.8K 4.6K
Gate Count 90K about 50K
Simulation Time 450 mins/frame 19 mins/frame
Detailed Design 3360 man-hours 1512 man-hours
Design Duration 4 months 3 months
fig. 1) Raytheon metrics comparing RTL vs. Behavioral design approaches.
The Empty Exhibit Hall
----------------------
Most of the time the 18 vendor exhibit hall was a bowling alley completely
free of customers. It was such a ghost town, even the EDA salesmen
themselves eventually ran out of industry gossip and sports stories to share
because they had been so recycled with those in the room. (It even got to
the point where Fred Stones of Summit Design announced the birth of his son
from ten days earlier just to have a new story. Micheal Andrew Stones, 7 lbs
14 oz.) More than once when I walked into a vendor's booth I would be met
by a suddenly rejoicing tech/sales staff because it meant that they'd finally
get to give at least one demo that day!
In the Cadence booth I found the salesdroids bubbling over what they were
reading in the EuroDAC '95 proceedings. What we both saw looking over the
proceedings was a no-nonsense user-driven benchmark done by an engineer at
Siemens (Eugen Rohm) that used large and realistic test models (like 8051's
and "KOM", a 41160 lines of code telecom ASIC) showing Leapfrog 2.1 kicked
butt! My kudos to the Cadence Leapfrog R&D team. Job well done.
Synopsys IKOS Model Tech Vantage Cadence Zycad
DESIGN V3.2 / V3.0a V1.41 V4.2 V5.0 Leapfrog 2.1 ViP 2.1
-------------------------------------------------------------------------
VSK 2.1 / 1.3 1.0 2.0 1.1 1.0 *
8051 * / 4.4 3.9 2.5 4.6 1.0 *
LCD 1.1 / 3.5 2.7 1.7 3.1 1.0 0.3
BADGE * / 8.0 16.9 4.5 3.6 1.0 *
DIVI 6.3 / 17.9 8.1 5.7 7.0 1.0 4.8
INV1000 2.7 / 4.3 1.7 1.3 1.6 1.0 0.3
KOM 4.6 / 12.3 6.0 4.8 4.6 1.0 *
SIG 3.6 / 31.7 * 2.6 5.2 1.0 0.4
SPARC 1.0 / 11.8 1.8 2.2 3.3 1.3 0.3
-------------------------------------------------------------------------
fig. 2) Siemens VHDL benchmark simulation run times normalized to the
fastest software simulator. ("*" - design could not be simulated.)
The Gossip & News
-----------------
SpeedSim's CEO, Don McInnis, was pleased to be beta-ing a Verilog front-end
reader to his SpeedSim/3 cycle-based simulator. (He plans to be working on a
VHDL front-end reader sometime later.) By design, SpeedSim/3 accelerates
gate models. Originally you had to use Synopsys to get to gates quickly for
SpeedSim/3 to work. By adding front-end readers, SpeedSim/3 loses its
dependence on Synopsys.
While ViewLogic was demo-ing their Verilog/VHDL co-simulator, what was more
interesting was my first look their cycle-based simulator, Ultraspec.
The i-Logix people were very tired going shuttle crazy because VIUF scheduled
on the exact same days that i-Logix scheduled their user's group meeting.
My Exemplar contacts were quite pleased with their recent 3.1 release, code
named the "ORCA release," because they added look-up table optimization to
support AT&T's ORCA FPGA's (which had the added side-effect of helping how
Exemplar synthesizes some Xilinx FPGA's.)
One of the more esoteric products I saw was VitalGen, a tool that generates
VITAL 3.0 complient libraries, from the VHDL Technology Group. Their CEO,
Bill Billowitch, was very active in creating the VITAL spec, so I'm sure
VitalGen will do its job well -- yet this $15,000 highly specialized software
will probably sell only about 30 to 50 copies because only the ASIC vendors
themselves would be interested in creating VITAL libraries.
The one new vendor face I saw at VIUF was Sand Microelectronics, a company
peddling a PCI performance analyzer and protocol/timing checker called "PPA."
By and far, the most interesting product I saw at the Boston VIUF was a
clever software concept made into a very, very useful hardware designer's
tool. This $12,000 tool from VEDA Design Automation is called VHDLCover.
VHDLCover determines if a set of functional test vectors you have exersizes
every part of your source code or not. It checks all the possible branches
plus all the possible conditions used to select branches plus all the
permutations of paths going through your source code. It's also useful
for checking state machines plus some race conditions and hazzards. (The
Verilog version is coming out in December.) I was very impressed. Either
phone (408) 496-4516 or e-mail "allen...@usveda.com" for more info.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant