Re: [beagleboard] BeagleBone connection to Dual Port Memory device

497 views
Skip to first unread message

Gerald Coley

unread,
Nov 29, 2012, 4:22:11 PM11/29/12
to beagl...@googlegroups.com
And why is GPMC not an option? What you describe is what the GPMC does. All of these functions should be available to you for use.

Gerald

On Thu, Nov 29, 2012 at 3:16 PM, Eric Feight <ejfe...@gmail.com> wrote:
I am currently looking for a way to connect a BeagleBone to a device whose interface is described as "comparable to implementing an 8 bit wide SRAM." It has 12 address lines (A0..A11), 8 data lines (D0..D7), Busy, IRQ, Output Enable, Write Enable and Chip Enable. Using GPMC doesn't appear to be an option. I've looked into pin muxing, but these lines do not seem to be readily available. Any insight would be greatly appreciated.

--
 
 



--
Gerald
 

Tom King

unread,
Nov 29, 2012, 5:29:00 PM11/29/12
to beagl...@googlegroups.com
unless you need more pins that usurp the GPMC bus pins that is the right way to do this.

Tom

Eric Feight

unread,
Dec 5, 2012, 4:27:21 PM12/5/12
to beagl...@googlegroups.com
Thanks for the response! I thought GPMC seemed like the way to go but I'm hitting a big gap in my knowledge here. This whole platform is completely new to me. Can you point me to documentation that would show me how to implement this, both from a hardware and software standpoint? My biggest stumbling block at this point is how do I physically build an interface between the header connectors on the BeagleBone and the device I'm trying to communicate with. Once I have that, I think I can figure out the software end of things by looking at GPMC sample code and the device documentation I have.

Jason Kridner

unread,
Dec 5, 2012, 5:34:10 PM12/5/12
to beagl...@googlegroups.com
On Wed, Dec 5, 2012 at 4:27 PM, Eric Feight <ejfe...@gmail.com> wrote:
> Thanks for the response! I thought GPMC seemed like the way to go but I'm
> hitting a big gap in my knowledge here. This whole platform is completely
> new to me. Can you point me to documentation that would show me how to
> implement this, both from a hardware and software standpoint?

http://engineersofthecorn.blogspot.com/2012/06/faux-gpmc-interfacing-with-beaglebone.html

> My biggest
> stumbling block at this point is how do I physically build an interface
> between the header connectors on the BeagleBone and the device I'm trying to
> communicate with. Once I have that, I think I can figure out the software
> end of things by looking at GPMC sample code and the device documentation I
> have.
>
>
> On Thursday, November 29, 2012 4:22:11 PM UTC-5, Gerald wrote:
>>
>> And why is GPMC not an option? What you describe is what the GPMC does.
>> All of these functions should be available to you for use.
>>
>> Gerald
>>
>>
>> On Thu, Nov 29, 2012 at 3:16 PM, Eric Feight <ejfe...@gmail.com> wrote:
>>>
>>> I am currently looking for a way to connect a BeagleBone to a device
>>> whose interface is described as "comparable to implementing an 8 bit wide
>>> SRAM." It has 12 address lines (A0..A11), 8 data lines (D0..D7), Busy, IRQ,
>>> Output Enable, Write Enable and Chip Enable. Using GPMC doesn't appear to be
>>> an option. I've looked into pin muxing, but these lines do not seem to be
>>> readily available. Any insight would be greatly appreciated.
>>>
>>> --
>>>
>>>
>>
>>
>>
>>
>> --
>> Gerald
>>
>> ger...@beagleboard.org
>> g-co...@ti.com
>> http://beagleboard.org/
>> http://circuitco.com/support/
>>
> --
>
>

Gerald Coley

unread,
Dec 12, 2012, 11:32:26 AM12/12/12
to beagl...@googlegroups.com
I have no such links that I can provide. You can try posting the request on the TI e2e list and see if someone has an example for you.

Gerald


On Wed, Dec 12, 2012 at 10:27 AM, Andy St John <andy....@gmail.com> wrote:
Gerald,

Could you please provide a (link to) C/C++ sample that performs simple read/write tasks using the gpmc bus?

Thank you,
Andy


On Thursday, November 29, 2012 4:16:15 PM UTC-5, Eric Feight wrote:
I am currently looking for a way to connect a BeagleBone to a device whose interface is described as "comparable to implementing an 8 bit wide SRAM." It has 12 address lines (A0..A11), 8 data lines (D0..D7), Busy, IRQ, Output Enable, Write Enable and Chip Enable. Using GPMC doesn't appear to be an option. I've looked into pin muxing, but these lines do not seem to be readily available. Any insight would be greatly appreciated.

--
For more options, visit http://beagleboard.org/discuss
 
 

Dr. Michael J. Chudobiak

unread,
Dec 12, 2012, 11:49:11 AM12/12/12
to beagl...@googlegroups.com
On 12/12/2012 11:27 AM, Andy St John wrote:
> Gerald,
>
> Could you please provide a (link to) C/C++ sample that performs simple
> read/write tasks using the gpmc bus?

An example file is attached, which shows how to access both the gpio and
gpmc I/O features.

You'll need to modify it for your own application - some of it is
specific to my configuration.

- Mike
bus.c
Reply all
Reply to author
Forward
0 new messages