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Modification to Buildroot 2016.11 needed to support Ethernet, USB and I2C in OrangePiPC - kernel changed to 4.9

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Wojciech Zabołotny

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Dec 15, 2016, 9:46:28 PM12/15/16
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Below are the source files of the modifications needed to get Ethernet, USB, GPIO and I2C support
for OrangePi PC in Linux compiled with Buildroot 2016.11

The version sent previously provided correct operation of Ethernet MAC, and USB, but
the GPIO and I2C controllers were not handled correctly.
According to http://linux-sunxi.org/Linux_mainlining_effort , GPIO and I2C should
work correctly with kernel 4.9.x . Therefore, I have decided to change the
kernel version, to the v4.9, that is currently "mainline" version.

The DTS files contained in the 4.9 kernel required only adding the Ethernet MAC
and turning on the I2C0 controller - to access I2C bus driven by pins PA12 and PA11.

Of course again it was necessary to add the sun8i-emac.c driver, available from:
https://github.com/montjoie/linux/blob/sun8i-emac-wip/drivers/net/ethernet/allwinner/sun8i-emac.c

The driver sun8i-emac.c contains the MODULE_LICENSE("GPL") declaration,
so I assume that it may be published according to the GPL license.
I hope to submit that modification to the offcial Buildroot tree after cleanup.
Anyway I hope, that it may be useful for some people even in that form.
To use that code, you should unpack Buldroot 2016.11 in a certain directory
and run "make orangepipc_defconfig". Then you shoul unpack this shar archive
in the same directory - it will add directiories with kernel patches
and sources of the Ethernet driver. It will also add the new BR package
"sun8i-emac-module".
You should manually modify the package/Config.in file, adding the reference
to the new package:
source "package/sun8i-emac-module/Config.in"
To add it in a chosen position in "Target packages" section.

Now you should run "make menuconfig" and:
1. In section "Kernel/Custom kernel patches" set (../kernel_patches)
2. In section "Target packages" select the "sun8i-emac-module"
3. In section "Kernel/Kernel version" change (4.7.3) to (4.9)

After that you can configure Buildroot according to your needs, and build the
Linux image.

DISCLAIMER: I DO NOT PROVIDE ANY WARRANTY. THE ABOVE MODIFICATION WORKED
FOR ME, BUT YOU CAN USE IT ONLY ON YOUR OWN RISK!
MAYBE IN CERTAIN CONDITIONS IT MAY DESTROY YOUR HARDWARE OR CAUSE OTHER
DAMAGE.

Good luck!
With best regards,
Wojtek

#!/bin/sh
# This is a shell archive (produced by GNU sharutils 4.15.2).
# To extract the files from this archive, save it to some FILE, remove
# everything before the '#!/bin/sh' line above, then type 'sh FILE'.
#
lock_dir=_sh31332
# Made on 2016-12-16 03:40 CET by <wzab@wzab>.
# Source directory was '/tmp/mmm'.
#
# Existing files will *not* be overwritten, unless '-c' is specified.
#
# This shar contains:
# length mode name
# ------ ---------- ------------------------------------------
# 2690 -rw-r--r-- kernel_patches/0001-Added-support-for-Ethernet-MAC.patch
# 525 -rw-r--r-- sun8i/Makefile
# 49859 -rw-r--r-- sun8i/sun8i-emac.c
# 336 -rw-r--r-- buildroot-2016.11/package/sun8i-emac-module/Config.in
# 651 -rw-r--r-- buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk
#
MD5SUM=${MD5SUM-md5sum}
f=`${MD5SUM} --version | egrep '^md5sum .*(core|text)utils'`
test -n "${f}" && md5check=true || md5check=false
${md5check} || \
echo 'Note: not verifying md5sums. Consider installing GNU coreutils.'
if test "X$1" = "X-c"
then keep_file=''
else keep_file=true
fi
echo=echo
save_IFS="${IFS}"
IFS="${IFS}:"
gettext_dir=
locale_dir=
set_echo=false

for dir in $PATH
do
if test -f $dir/gettext \
&& ($dir/gettext --version >/dev/null 2>&1)
then
case `$dir/gettext --version 2>&1 | sed 1q` in
*GNU*) gettext_dir=$dir
set_echo=true
break ;;
esac
fi
done

if ${set_echo}
then
set_echo=false
for dir in $PATH
do
if test -f $dir/shar \
&& ($dir/shar --print-text-domain-dir >/dev/null 2>&1)
then
locale_dir=`$dir/shar --print-text-domain-dir`
set_echo=true
break
fi
done

if ${set_echo}
then
TEXTDOMAINDIR=$locale_dir
export TEXTDOMAINDIR
TEXTDOMAIN=sharutils
export TEXTDOMAIN
echo="$gettext_dir/gettext -s"
fi
fi
IFS="$save_IFS"
if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null
then if (echo -n test; echo 1,2,3) | grep n >/dev/null
then shar_n= shar_c='
'
else shar_n=-n shar_c= ; fi
else shar_n= shar_c='\c' ; fi
f=shar-touch.$$
st1=200112312359.59
st2=123123592001.59
st2tr=123123592001.5 # old SysV 14-char limit
st3=1231235901

if touch -am -t ${st1} ${f} >/dev/null 2>&1 && \
test ! -f ${st1} && test -f ${f}; then
shar_touch='touch -am -t $1$2$3$4$5$6.$7 "$8"'

elif touch -am ${st2} ${f} >/dev/null 2>&1 && \
test ! -f ${st2} && test ! -f ${st2tr} && test -f ${f}; then
shar_touch='touch -am $3$4$5$6$1$2.$7 "$8"'

elif touch -am ${st3} ${f} >/dev/null 2>&1 && \
test ! -f ${st3} && test -f ${f}; then
shar_touch='touch -am $3$4$5$6$2 "$8"'

else
shar_touch=:
echo
${echo} 'WARNING: not restoring timestamps. Consider getting and
installing GNU '\''touch'\'', distributed in GNU coreutils...'
echo
fi
rm -f ${st1} ${st2} ${st2tr} ${st3} ${f}
#
if test ! -d ${lock_dir} ; then :
else ${echo} "lock directory ${lock_dir} exists"
exit 1
fi
if mkdir ${lock_dir}
then ${echo} "x - created lock directory ${lock_dir}."
else ${echo} "x - failed to create lock directory ${lock_dir}."
exit 1
fi
# ============= kernel_patches/0001-Added-support-for-Ethernet-MAC.patch ==============
if test ! -d 'kernel_patches'; then
mkdir 'kernel_patches'
if test $? -eq 0
then ${echo} "x - created directory kernel_patches."
else ${echo} "x - failed to create directory kernel_patches."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'kernel_patches/0001-Added-support-for-Ethernet-MAC.patch'
then
${echo} "x - SKIPPING kernel_patches/0001-Added-support-for-Ethernet-MAC.patch (file already exists)"

else
${echo} "x - extracting kernel_patches/0001-Added-support-for-Ethernet-MAC.patch (text)"
sed 's/^X//' << 'SHAR_EOF' > 'kernel_patches/0001-Added-support-for-Ethernet-MAC.patch' &&
XFrom 284397e8ce76b15870670438157a309583a013de Mon Sep 17 00:00:00 2001
XFrom: "Wojciech M. Zabolotny" <wza...@gmail.com>
Date: Fri, 16 Dec 2016 00:20:01 +0100
Subject: [PATCH] Added support for Ethernet MAC
X
---
X arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 12 ++++++++++
X arch/arm/boot/dts/sun8i-h3.dtsi | 35 ++++++++++++++++++++++++++++++
X 2 files changed, 47 insertions(+)
X
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 3ec9712..fd708d0 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -183,3 +183,18 @@
X /* USB VBUS is always on */
X status = "okay";
X };
+
+&emac {
+ phy = <&phy1>;
+ phy-mode = "mii";
+ allwinner,use-internal-phy;
+ allwinner,leds-active-low;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+&i2c0 {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index f4ba088..126bf87 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -50,6 +50,10 @@
X / {
X interrupt-parent = <&gic>;
X
+ aliases {
+ ethernet0 = &emac;
+ };
+
X cpus {
X #address-cells = <1>;
X #size-cells = <0>;
@@ -140,6 +144,12 @@
X #size-cells = <1>;
X ranges;
X
+ syscon: syscon@01c00000 {
+ compatible = "allwinner,sun8i-h3-syscon","syscon";
+ reg = <0x01c00000 0x34>;
+ };
+
+
X dma: dma-controller@01c02000 {
X compatible = "allwinner,sun8i-h3-dma";
X reg = <0x01c02000 0x1000>;
@@ -348,6 +358,17 @@
X allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
X };
X
+ emac_rgmii_pins: emac0@0 {
+ allwinner,pins = "PD0", "PD1", "PD2", "PD3",
+ "PD4", "PD5", "PD7",
+ "PD8", "PD9", "PD10",
+ "PD12", "PD13", "PD15",
+ "PD16", "PD17";
+ allwinner,function = "emac";
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
X mmc0_pins_a: mmc0@0 {
X allwinner,pins = "PF0", "PF1", "PF2", "PF3",
X "PF4", "PF5";
@@ -530,6 +551,20 @@
X #size-cells = <0>;
X };
X
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
+ reg-names = "emac", "syscon";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
+ reset-names = "ahb", "ephy";
+ clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
+ clock-names = "ahb", "ephy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
X gic: interrupt-controller@01c81000 {
X compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
X reg = <0x01c81000 0x1000>,
--
2.10.2
X
SHAR_EOF
(set 20 16 12 16 03 29 47 'kernel_patches/0001-Added-support-for-Ethernet-MAC.patch'
eval "${shar_touch}") && \
chmod 0644 'kernel_patches/0001-Added-support-for-Ethernet-MAC.patch'
if test $? -ne 0
then ${echo} "restore of kernel_patches/0001-Added-support-for-Ethernet-MAC.patch failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'kernel_patches/0001-Added-support-for-Ethernet-MAC.patch': 'MD5 check failed'
) << \SHAR_EOF
a902f47e340e74de226f6a289546d183 kernel_patches/0001-Added-support-for-Ethernet-MAC.patch
SHAR_EOF

else
test `LC_ALL=C wc -c < 'kernel_patches/0001-Added-support-for-Ethernet-MAC.patch'` -ne 2690 && \
${echo} "restoration warning: size of 'kernel_patches/0001-Added-support-for-Ethernet-MAC.patch' is not 2690"
fi
fi
# ============= sun8i/Makefile ==============
if test ! -d 'sun8i'; then
mkdir 'sun8i'
if test $? -eq 0
then ${echo} "x - created directory sun8i."
else ${echo} "x - failed to create directory sun8i."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'sun8i/Makefile'
then
${echo} "x - SKIPPING sun8i/Makefile (file already exists)"

else
${echo} "x - extracting sun8i/Makefile (text)"
sed 's/^X//' << 'SHAR_EOF' > 'sun8i/Makefile' &&
# If KERNELRELEASE is defined, we've been invoked from the
# kernel build system and can use its language.
ifneq ($(KERNELRELEASE),)
X obj-m := sun8i-emac.o
# Otherwise we were called directly from the command
# line; invoke the kernel build system.
else
X KERNELDIR ?= /lib/modules/$(shell uname -r)/build
X PWD := $(shell pwd)
default:
X $(MAKE) -C $(KERNELDIR) M=$(PWD) modules
X
modules_install:
X $(MAKE) -C $(KERNELDIR) M=$(PWD) modules_install
X
clean:
X $(MAKE) -C $(KERNELDIR) M=$(PWD) clean
X
endif
X
SHAR_EOF
(set 20 16 12 10 00 19 54 'sun8i/Makefile'
eval "${shar_touch}") && \
chmod 0644 'sun8i/Makefile'
if test $? -ne 0
then ${echo} "restore of sun8i/Makefile failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'sun8i/Makefile': 'MD5 check failed'
) << \SHAR_EOF
282e309dfc573669bd5846e44d7a82bd sun8i/Makefile
SHAR_EOF

else
test `LC_ALL=C wc -c < 'sun8i/Makefile'` -ne 525 && \
${echo} "restoration warning: size of 'sun8i/Makefile' is not 525"
fi
fi
# ============= sun8i/sun8i-emac.c ==============
if test ! -d 'sun8i'; then
mkdir 'sun8i'
if test $? -eq 0
then ${echo} "x - created directory sun8i."
else ${echo} "x - failed to create directory sun8i."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'sun8i/sun8i-emac.c'
then
${echo} "x - SKIPPING sun8i/sun8i-emac.c (file already exists)"

else
${echo} "x - extracting sun8i/sun8i-emac.c (text)"
sed 's/^X//' << 'SHAR_EOF' > 'sun8i/sun8i-emac.c' &&
/*
X * sun8i-emac driver
X *
X * Copyright (C) 2015-2016 Corentin LABBE <clabbe....@gmail.com>
X *
X * This is the driver for Allwinner Ethernet MAC found in H3/A83T/A64 SoC
X *
X * TODO:
X * - NAPI
X * - MAC filtering
X * - Jumbo frame
X * - features rx-all (NETIF_F_RXALL_BIT)
X */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/mii.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/scatterlist.h>
#include <linux/skbuff.h>
X
#define SUN8I_EMAC_BASIC_CTL0 0x00
#define SUN8I_EMAC_BASIC_CTL1 0x04
X
#define SUN8I_EMAC_MDIO_CMD 0x48
#define SUN8I_EMAC_MDIO_DATA 0x4C
X
#define SUN8I_EMAC_RX_CTL0 0x24
#define SUN8I_EMAC_RX_CTL1 0x28
X
#define SUN8I_EMAC_TX_CTL0 0x10
#define SUN8I_EMAC_TX_CTL1 0x14
X
#define SUN8I_EMAC_TX_FLOW_CTL 0x1C
X
#define SUN8I_EMAC_RX_FRM_FLT 0x38
X
#define SUN8I_EMAC_INT_STA 0x08
#define SUN8I_EMAC_INT_EN 0x0C
#define SUN8I_EMAC_RGMII_STA 0xD0
X
#define SUN8I_EMAC_TX_DMA_STA 0xB0
#define SUN8I_EMAC_TX_CUR_DESC 0xB4
#define SUN8I_EMAC_TX_CUR_BUF 0xB8
#define SUN8I_EMAC_RX_DMA_STA 0xC0
X
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
#define MDIO_CMD_MII_PHY_REG_ADDR_MASK GENMASK(8, 4)
#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
#define MDIO_CMD_MII_PHY_ADDR_MASK GENMASK(16, 12)
#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
X
#define SUN8I_EMAC_MACADDR_HI 0x50
#define SUN8I_EMAC_MACADDR_LO 0x54
X
#define SUN8I_EMAC_RX_DESC_LIST 0x34
#define SUN8I_EMAC_TX_DESC_LIST 0x20
X
#define SUN8I_EMAC_TX_DO_CRC (BIT(27) | BIT(28))
#define SUN8I_EMAC_RX_DO_CRC BIT(27)
#define SUN8I_EMAC_RX_STRIP_FCS BIT(28)
X
#define SUN8I_COULD_BE_USED_BY_DMA BIT(31)
X
#define FLOW_RX 1
#define FLOW_TX 2
X
/* describe how data from skb are DMA mapped */
#define MAP_SINGLE 1
#define MAP_PAGE 2
X
enum emac_variant {
X A83T_EMAC,
X H3_EMAC,
X A64_EMAC,
};
X
struct ethtool_str {
X char name[ETH_GSTRING_LEN];
};
X
static const struct ethtool_str estats_str[] = {
X /* errors */
X { "rx_payload_error" },
X { "rx_CRC_error" },
X { "rx_phy_error" },
X { "rx_length_error" },
X { "rx_col_error" },
X { "rx_header_error" },
X { "rx_overflow_error" },
X { "rx_saf_error" },
X { "rx_daf_error" },
X { "rx_buf_error" },
X /* misc infos */
X { "tx_stop_queue" },
X { "rx_dma_ua" },
X { "rx_dma_stop" },
X { "tx_dma_ua" },
X { "tx_dma_stop" },
X { "rx_hw_csum" },
X { "tx_hw_csum" },
X /* interrupts */
X { "rx_early_int" },
X { "tx_early_int" },
X { "tx_underflow_int" },
X /* debug */
X { "tx_used_desc" },
};
X
struct sun8i_emac_stats {
X u64 rx_payload_error;
X u64 rx_crc_error;
X u64 rx_phy_error;
X u64 rx_length_error;
X u64 rx_col_error;
X u64 rx_header_error;
X u64 rx_overflow_error;
X u64 rx_saf_fail;
X u64 rx_daf_fail;
X u64 rx_buf_error;
X
X u64 tx_stop_queue;
X u64 rx_dma_ua;
X u64 rx_dma_stop;
X u64 tx_dma_ua;
X u64 tx_dma_stop;
X u64 rx_hw_csum;
X u64 tx_hw_csum;
X
X u64 rx_early_int;
X u64 tx_early_int;
X u64 tx_underflow_int;
X u64 tx_used_desc;
};
X
/* The datasheet said that each descriptor can transfers up to 4096bytes
X * But latter, a register documentation reduce that value to 2048
X * Anyway using 2048 cause strange behaviours and even BSP driver use 2047
X */
#define DESC_BUF_MAX 2044
#if (DESC_BUF_MAX < (ETH_FRAME_LEN + 4))
#error "DESC_BUF_MAX must be set at minimum to ETH_FRAME_LEN + 4"
#endif
X
/* MAGIC value for knowing if a descriptor is available or not */
#define DCLEAN (BIT(16) | BIT(14) | BIT(12) | BIT(10) | BIT(9))
X
/* Structure of DMA descriptor used by the hardware */
struct dma_desc {
X u32 status; /* status of the descriptor */
X u32 st; /* Information on the frame */
X u32 buf_addr; /* physical address of the frame data */
X u32 next; /* physical address of next dma_desc */
} __packed __aligned(4);
X
/* Benched on OPIPC with 100M, setting more than 256 does not give any
X * perf boost
X */
static int nbdesc_tx = 256;
module_param(nbdesc_tx, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(nbdesc_tx, "Number of descriptors in the TX list");
static int nbdesc_rx = 128;
module_param(nbdesc_rx, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(nbdesc_rx, "Number of descriptors in the RX list");
X
struct sun8i_emac_priv {
X void __iomem *base;
X void __iomem *syscon;
X int irq;
X struct device *dev;
X struct net_device *ndev;
X struct mii_bus *mdio;
X spinlock_t lock;/* for adjust_link */
X spinlock_t tx_lock;/* control the access of transmit descriptors */
X int duplex;
X int speed;
X int link;
X int phy_interface;
X enum emac_variant variant;
X struct device_node *phy_node;
X struct clk *ahb_clk;
X struct clk *ephy_clk;
X struct regulator *regulator;
X struct regulator *regulator_io;
X bool use_internal_phy;
X
X struct reset_control *rst;
X struct reset_control *rst_ephy;
X
X struct dma_desc *dd_rx __aligned(4);
X dma_addr_t dd_rx_phy __aligned(4);
X struct dma_desc *dd_tx __aligned(4);
X dma_addr_t dd_tx_phy __aligned(4);
X struct sk_buff **rx_sk;
X struct sk_buff **tx_sk;
X int *tx_map;
X
X int tx_slot;
X int tx_dirty;
X int rx_dirty;
X struct sun8i_emac_stats estats;
X u32 msg_enable;
X int flow_ctrl;
X int pause;
};
X
static void rb_inc(int *p, const int max)
{
X (*p)++;
X if (*p >= max)
X *p = 0;
}
X
/* Return the number of contiguous free descriptors
X * starting from tx_slot
X */
static int rb_tx_numfreedesc(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X
X if (priv->tx_slot < priv->tx_dirty)
X return priv->tx_dirty - priv->tx_slot;
X
X return (nbdesc_tx - priv->tx_slot) + priv->tx_dirty;
}
X
/* Allocate a skb in a DMA descriptor
X *
X * @i index of slot to fill
*/
static int sun8i_emac_rx_sk(struct net_device *ndev, int i)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct dma_desc *ddesc;
X struct sk_buff *sk;
X
X ddesc = priv->dd_rx + i;
X
X ddesc->st = 0;
X
X sk = netdev_alloc_skb_ip_align(ndev, DESC_BUF_MAX);
X if (!sk)
X return -ENOMEM;
X
X /* should not happen */
X if (unlikely(priv->rx_sk[i]))
X dev_warn(priv->dev, "BUG: Leaking a skbuff\n");
X
X priv->rx_sk[i] = sk;
X
X ddesc->buf_addr = dma_map_single(priv->dev, sk->data,
X DESC_BUF_MAX, DMA_FROM_DEVICE);
X if (dma_mapping_error(priv->dev, ddesc->buf_addr)) {
X dev_err(priv->dev, "ERROR: Cannot dma_map RX buffer\n");
X dev_kfree_skb(sk);
X return -EFAULT;
X }
X ddesc->st |= DESC_BUF_MAX;
X ddesc->status = BIT(31);
X
X return 0;
}
X
/* Set MAC address for slot index
X * @addr: the MAC address to set
X * @index: The index of slot where to set address.
X * The slot 0 is the main MACaddr
X */
static void sun8i_emac_set_macaddr(struct sun8i_emac_priv *priv,
X const u8 *addr, int index)
{
X u32 v;
X
X dev_info(priv->dev, "device MAC address slot %d %02x:%02x:%02x:%02x:%02x:%02x\n",
X index, addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
X
X v = (addr[5] << 8) | addr[4];
X writel(v, priv->base + SUN8I_EMAC_MACADDR_HI + index * 8);
X v = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
X writel(v, priv->base + SUN8I_EMAC_MACADDR_LO + index * 8);
}
X
static void sun8i_emac_set_link_mode(struct sun8i_emac_priv *priv)
{
X u32 v;
X
X v = readl(priv->base + SUN8I_EMAC_BASIC_CTL0);
X
X if (priv->duplex)
X v |= BIT(0);
X else
X v &= ~BIT(0);
X
X v &= ~0x0C;
X switch (priv->speed) {
X case 1000:
X break;
X case 100:
X v |= BIT(2);
X v |= BIT(3);
X break;
X case 10:
X v |= BIT(3);
X break;
X }
X
X writel(v, priv->base + SUN8I_EMAC_BASIC_CTL0);
}
X
static void sun8i_emac_flow_ctrl(struct sun8i_emac_priv *priv, int duplex,
X int fc, int pause)
{
X u32 flow = 0;
X
X netif_dbg(priv, link, priv->ndev, "%s %d %d %d\n", __func__,
X duplex, fc, pause);
X
X flow = readl(priv->base + SUN8I_EMAC_RX_CTL0);
X if (fc & FLOW_RX)
X flow |= BIT(16);
X else
X flow &= ~BIT(16);
X writel(flow, priv->base + SUN8I_EMAC_RX_CTL0);
X
X flow = readl(priv->base + SUN8I_EMAC_TX_FLOW_CTL);
X if (fc & FLOW_TX)
X flow |= BIT(0);
X else
X flow &= ~BIT(0);
X writel(flow, priv->base + SUN8I_EMAC_TX_FLOW_CTL);
}
X
/* Grab a frame into a skb from descriptor number i */
static int sun8i_emac_rx_from_ddesc(struct net_device *ndev, int i)
{
X struct sk_buff *skb;
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct dma_desc *ddesc = priv->dd_rx + i;
X int frame_len;
X int crc_checked = 0;
X
X if (ndev->features & NETIF_F_RXCSUM)
X crc_checked = 1;
X
X /* bit0/bit7 work only on IPv4/IPv6 TCP traffic,
X * (not on ARP for example) so we dont raise rx_errors/discard frame
X */
X /* the checksum or length of received frame's payload is wrong*/
X if (ddesc->status & BIT(0)) {
X priv->estats.rx_payload_error++;
X crc_checked = 0;
X }
X if (ddesc->status & BIT(1)) {
X priv->ndev->stats.rx_errors++;
X priv->ndev->stats.rx_crc_errors++;
X priv->estats.rx_crc_error++;
X goto discard_frame;
X }
X if ((ddesc->status & BIT(3))) {
X priv->ndev->stats.rx_errors++;
X priv->estats.rx_phy_error++;
X goto discard_frame;
X }
X if ((ddesc->status & BIT(4))) {
X priv->ndev->stats.rx_errors++;
X priv->ndev->stats.rx_length_errors++;
X priv->estats.rx_length_error++;
X goto discard_frame;
X }
X if ((ddesc->status & BIT(6))) {
X priv->ndev->stats.rx_errors++;
X priv->estats.rx_col_error++;
X goto discard_frame;
X }
X if ((ddesc->status & BIT(7))) {
X priv->estats.rx_header_error++;
X crc_checked = 0;
X }
X if ((ddesc->status & BIT(11))) {
X priv->ndev->stats.rx_over_errors++;
X priv->estats.rx_overflow_error++;
X goto discard_frame;
X }
X if ((ddesc->status & BIT(14))) {
X priv->ndev->stats.rx_errors++;
X priv->estats.rx_buf_error++;
X goto discard_frame;
X }
X
X if ((ddesc->status & BIT(9)) == 0) {
X /* begin of a Jumbo frame */
X dev_warn(priv->dev, "This should not happen\n");
X goto discard_frame;
X }
X frame_len = (ddesc->status >> 16) & 0x3FFF;
X if (!(ndev->features & NETIF_F_RXFCS))
X frame_len -= ETH_FCS_LEN;
X
X skb = priv->rx_sk[i];
X
X netif_dbg(priv, rx_status, priv->ndev,
X "%s from %02d %pad len=%d status=%x st=%x\n",
X __func__, i, &ddesc, frame_len, ddesc->status, ddesc->st);
X
X skb_put(skb, frame_len);
X
X dma_unmap_single(priv->dev, ddesc->buf_addr, DESC_BUF_MAX,
X DMA_FROM_DEVICE);
X skb->protocol = eth_type_trans(skb, priv->ndev);
X if (crc_checked) {
X skb->ip_summed = CHECKSUM_UNNECESSARY;
X priv->estats.rx_hw_csum++;
X } else {
X skb->ip_summed = CHECKSUM_PARTIAL;
X }
X skb->dev = priv->ndev;
X
X priv->ndev->stats.rx_packets++;
X priv->ndev->stats.rx_bytes += frame_len;
X priv->rx_sk[i] = NULL;
X
X /* this frame is not the last */
X if ((ddesc->status & BIT(8)) == 0) {
X dev_warn(priv->dev, "Multi frame not implemented currlen=%d\n",
X frame_len);
X }
X
X sun8i_emac_rx_sk(ndev, i);
X
X netif_rx(skb);
X
X return 0;
X /* If the frame need to be dropped, we simply reuse the buffer */
discard_frame:
X ddesc->st = DESC_BUF_MAX;
X ddesc->status = BIT(31);
X return 0;
}
X
/* Cycle over RX DMA descriptors for finding frame to receive
X */
static int sun8i_emac_receive_all(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct dma_desc *ddesc;
X
X ddesc = priv->dd_rx + priv->rx_dirty;
X while (!(ddesc->status & BIT(31))) {
X sun8i_emac_rx_from_ddesc(ndev, priv->rx_dirty);
X rb_inc(&priv->rx_dirty, nbdesc_rx);
X ddesc = priv->dd_rx + priv->rx_dirty;
X };
X
X return 0;
}
X
/* iterate over dma_desc for finding completed xmit.
X * Called from interrupt context, so no need to spinlock tx
X *
X * The problem is: how to know that a descriptor is sent and not just in
X * preparation.
X * Need to have status=0 and st set but this is the state of first frame just
X * before setting the own-by-DMA bit.
X * The solution is to used the artificial value DCLEAN.
X */
static int sun8i_emac_complete_xmit(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct dma_desc *ddesc;
X int frame_len;
X
X do {
X ddesc = priv->dd_tx + priv->tx_dirty;
X
X if (ddesc->status & BIT(31)) {
X dev_info(priv->dev, "BUG: DMA still set %d %d\n",
X priv->tx_dirty, priv->tx_slot);
X return 0;
X }
X
X if (ddesc->status == DCLEAN)
X return 0;
X
X if (ddesc->status == 0 && !ddesc->st) {
X dev_info(priv->dev, "BUG: reached the void %d %d\n",
X priv->tx_dirty, priv->tx_slot);
X return 0;
X }
X
X /* TX_UNDERFLOW_ERR */
X if (ddesc->status & BIT(1))
X priv->ndev->stats.tx_errors++;
X /* TX_DEFER_ERR */
X if (ddesc->status & BIT(2))
X priv->ndev->stats.tx_errors++;
X /* BIT 6:3 numbers of collisions */
X if (ddesc->status & 0x78)
X priv->ndev->stats.collisions +=
X (ddesc->status & 0x78) >> 3;
X /* TX_COL_ERR_1 */
X if (ddesc->status & BIT(8))
X priv->ndev->stats.tx_errors++;
X /* TX_COL_ERR_0 */
X if (ddesc->status & BIT(9))
X priv->ndev->stats.tx_errors++;
X /* TX_CRS_ERR */
X if (ddesc->status & BIT(10))
X priv->ndev->stats.tx_carrier_errors++;
X /* TX_PAYLOAD_ERR */
X if (ddesc->status & BIT(12))
X priv->ndev->stats.tx_errors++;
X /* TX_LENGTH_ERR */
X if (ddesc->status & BIT(14))
X priv->ndev->stats.tx_errors++;
X /* TX_HEADER_ERR */
X if (ddesc->status & BIT(16))
X priv->ndev->stats.tx_errors++;
X frame_len = ddesc->st & 0x3FFF;
X if (priv->tx_map[priv->tx_dirty] == MAP_SINGLE)
X dma_unmap_single(priv->dev, ddesc->buf_addr,
X frame_len, DMA_TO_DEVICE);
X else
X dma_unmap_page(priv->dev, ddesc->buf_addr,
X frame_len, DMA_TO_DEVICE);
X /* we can free skb only on last frame */
X if (priv->tx_sk[priv->tx_dirty] && (ddesc->st & BIT(30)))
X dev_kfree_skb_irq(priv->tx_sk[priv->tx_dirty]);
X
X priv->tx_sk[priv->tx_dirty] = NULL;
X priv->tx_map[priv->tx_dirty] = 0;
X ddesc->status = DCLEAN;
X ddesc->st = 0;
X
X rb_inc(&priv->tx_dirty, nbdesc_tx);
X ddesc = priv->dd_tx + priv->tx_dirty;
X } while (ddesc->st && !(ddesc->status & BIT(31)));
X
X if (netif_queue_stopped(ndev) &&
X rb_tx_numfreedesc(ndev) > MAX_SKB_FRAGS + 1)
X netif_wake_queue(ndev);
X
X return 0;
}
X
static int sun8i_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
{
X struct net_device *ndev = bus->priv;
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X int err;
X u32 reg;
X
X err = readl_poll_timeout(priv->base + SUN8I_EMAC_MDIO_CMD, reg,
X !(reg & MDIO_CMD_MII_BUSY), 100, 10000);
X if (err) {
X dev_err(priv->dev, "%s timeout %x\n", __func__, reg);
X return err;
X }
X
X reg &= ~MDIO_CMD_MII_WRITE;
X reg &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
X reg |= (phy_reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
X MDIO_CMD_MII_PHY_REG_ADDR_MASK;
X
X reg &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
X
X reg |= (phy_addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
X MDIO_CMD_MII_PHY_ADDR_MASK;
X
X reg |= MDIO_CMD_MII_BUSY;
X
X writel(reg, priv->base + SUN8I_EMAC_MDIO_CMD);
X
X err = readl_poll_timeout(priv->base + SUN8I_EMAC_MDIO_CMD, reg,
X !(reg & MDIO_CMD_MII_BUSY), 100, 10000);
X
X if (err) {
X dev_err(priv->dev, "%s timeout %x\n", __func__, reg);
X return err;
X }
X
X return readl(priv->base + SUN8I_EMAC_MDIO_DATA);
}
X
static int sun8i_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg,
X u16 data)
{
X struct net_device *ndev = bus->priv;
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X u32 reg;
X int err;
X
X err = readl_poll_timeout(priv->base + SUN8I_EMAC_MDIO_CMD, reg,
X !(reg & MDIO_CMD_MII_BUSY), 100, 10000);
X if (err) {
X dev_err(priv->dev, "%s timeout %x\n", __func__, reg);
X return err;
X }
X
X reg &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
X reg |= (phy_reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
X MDIO_CMD_MII_PHY_REG_ADDR_MASK;
X
X reg &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
X reg |= (phy_addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
X MDIO_CMD_MII_PHY_ADDR_MASK;
X
X reg |= MDIO_CMD_MII_WRITE;
X reg |= MDIO_CMD_MII_BUSY;
X
X writel(reg, priv->base + SUN8I_EMAC_MDIO_CMD);
X writel(data, priv->base + SUN8I_EMAC_MDIO_DATA);
X dev_dbg(priv->dev, "%s %d %d %x %x\n", __func__, phy_addr, phy_reg,
X reg, data);
X
X err = readl_poll_timeout(priv->base + SUN8I_EMAC_MDIO_CMD, reg,
X !(reg & MDIO_CMD_MII_BUSY), 100, 10000);
X if (err) {
X dev_err(priv->dev, "%s timeout %x\n", __func__, reg);
X return err;
X }
X
X return 0;
}
X
static int sun8i_emac_mdio_register(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct mii_bus *bus;
X int ret;
X
X bus = devm_mdiobus_alloc(priv->dev);
X if (!bus) {
X netdev_err(ndev, "Failed to allocate new mdio bus\n");
X return -ENOMEM;
X }
X
X bus->name = dev_name(priv->dev);
X bus->read = &sun8i_mdio_read;
X bus->write = &sun8i_mdio_write;
X snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%x", bus->name, 0);
X
X bus->parent = priv->dev;
X bus->priv = ndev;
X
X ret = of_mdiobus_register(bus, priv->dev->of_node);
X if (ret) {
X netdev_err(ndev, "Could not register as MDIO bus: %d\n", ret);
X return ret;
X }
X
X priv->mdio = bus;
X
X return 0;
}
X
static void sun8i_emac_adjust_link(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct phy_device *phydev = ndev->phydev;
X unsigned long flags;
X int new_state = 0;
X
X netif_dbg(priv, link, priv->ndev,
X "%s link=%x duplex=%x speed=%x\n", __func__,
X phydev->link, phydev->duplex, phydev->speed);
X if (!phydev)
X return;
X
X spin_lock_irqsave(&priv->lock, flags);
X
X if (phydev->link) {
X if (phydev->duplex != priv->duplex) {
X new_state = 1;
X priv->duplex = phydev->duplex;
X }
X if (phydev->pause)
X sun8i_emac_flow_ctrl(priv, phydev->duplex,
X priv->flow_ctrl, priv->pause);
X
X if (phydev->speed != priv->speed) {
X new_state = 1;
X priv->speed = phydev->speed;
X }
X
X if (priv->link == 0) {
X new_state = 1;
X priv->link = phydev->link;
X }
X
X netif_dbg(priv, link, priv->ndev,
X "%s new=%d link=%d pause=%d\n",
X __func__, new_state, priv->link, phydev->pause);
X if (new_state)
X sun8i_emac_set_link_mode(priv);
X } else if (priv->link != phydev->link) {
X new_state = 1;
X priv->link = 0;
X priv->speed = 0;
X priv->duplex = -1;
X }
X
X if (new_state)
X phy_print_status(phydev);
X
X spin_unlock_irqrestore(&priv->lock, flags);
}
X
/* H3 specific bits for EPHY */
#define H3_EPHY_ADDR_SHIFT 20
#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
#define H3_EPHY_DEFAULT_VALUE 0x58000
#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
X
/* H3/A64 specific bits */
#define SC_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
X
/* Generic system control EMAC_CLK bits */
#define SC_ETXDC_MASK GENMASK(2, 0)
#define SC_ETXDC_SHIFT 10
#define SC_ERXDC_MASK GENMASK(4, 0)
#define SC_ERXDC_SHIFT 5
#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
#define SC_ETCS_MASK GENMASK(1, 0)
#define SC_ETCS_MII 0x0
#define SC_ETCS_EXT_GMII 0x1
#define SC_ETCS_INT_GMII 0x2
X
static int sun8i_emac_set_syscon_ephy(struct net_device *ndev, u32 *reg)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct device_node *node = priv->dev->of_node;
X int ret;
X
X *reg &= ~H3_EPHY_DEFAULT_MASK;
X *reg |= H3_EPHY_DEFAULT_VALUE;
X
X if (!priv->use_internal_phy) {
X /* switch to external PHY interface */
X *reg &= ~H3_EPHY_SELECT;
X return 0;
X }
X
X if (priv->phy_interface != PHY_INTERFACE_MODE_MII) {
X netdev_warn(ndev,
X "Internal PHY requested, forcing MII mode.\n");
X priv->phy_interface = PHY_INTERFACE_MODE_MII;
X }
X
X *reg |= H3_EPHY_SELECT;
X *reg &= ~H3_EPHY_SHUTDOWN;
X
X if (of_property_read_bool(node, "allwinner,leds-active-low"))
X *reg |= H3_EPHY_LED_POL;
X
X ret = of_mdio_parse_addr(priv->dev, priv->phy_node);
X if (ret < 0)
X return ret;
X
X /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
X * address. No need to mask it again.
X */
X *reg |= ret << H3_EPHY_ADDR_SHIFT;
X
X return 0;
}
X
static int sun8i_emac_set_syscon(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct device_node *node = priv->dev->of_node;
X int ret;
X u32 reg, val;
X
X reg = readl(priv->syscon);
X
X if (priv->variant == H3_EMAC) {
X ret = sun8i_emac_set_syscon_ephy(ndev, &reg);
X if (ret)
X return ret;
X }
X
X if (!of_property_read_u32(node, "allwinner,tx-delay", &val)) {
X if (val <= SC_ETXDC_MASK) {
X reg &= ~(SC_ETXDC_MASK << SC_ETXDC_SHIFT);
X reg |= (val << SC_ETXDC_SHIFT);
X } else {
X netdev_warn(ndev, "invalid TX clock delay: %d\n", val);
X }
X }
X
X if (!of_property_read_u32(node, "allwinner,rx-delay", &val)) {
X if (val <= SC_ERXDC_MASK) {
X reg &= ~(SC_ERXDC_MASK << SC_ERXDC_SHIFT);
X reg |= (val << SC_ERXDC_SHIFT);
X } else {
X netdev_warn(ndev, "invalid RX clock delay: %d\n", val);
X }
X }
X
X /* Clear interface mode bits */
X reg &= ~(SC_ETCS_MASK | SC_EPIT);
X if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
X reg &= ~SC_RMII_EN;
X
X switch (priv->phy_interface) {
X case PHY_INTERFACE_MODE_MII:
X /* default */
X break;
X case PHY_INTERFACE_MODE_RGMII:
X reg |= SC_EPIT | SC_ETCS_INT_GMII;
X break;
X case PHY_INTERFACE_MODE_RMII:
X if (priv->variant == H3_EMAC || priv->variant == A64_EMAC) {
X reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
X break;
X }
X /* RMII not supported on A83T */
X default:
X netdev_err(ndev, "unsupported interface mode: %s",
X phy_modes(priv->phy_interface));
X return -EINVAL;
X }
X
X writel(reg, priv->syscon);
X
X return 0;
}
X
static void sun8i_emac_unset_syscon(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X u32 reg = 0;
X
X if (priv->variant == H3_EMAC)
X reg = H3_EPHY_DEFAULT_VALUE;
X
X writel(reg, priv->syscon);
}
X
static void sun8i_emac_set_mdc(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X unsigned long rate;
X u32 reg;
X
X rate = clk_get_rate(priv->ahb_clk);
X if (rate > 160000000)
X reg = 0x3 << 20; /* AHB / 128 */
X else if (rate > 80000000)
X reg = 0x2 << 20; /* AHB / 64 */
X else if (rate > 40000000)
X reg = 0x1 << 20; /* AHB / 32 */
X else
X reg = 0x0 << 20; /* AHB / 16 */
X netif_dbg(priv, link, ndev, "MDC auto : %x\n", reg);
X writel(reg, priv->base + SUN8I_EMAC_MDIO_CMD);
}
X
static int sun8i_emac_init(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct device_node *node = priv->dev->of_node;
X const u8 *addr;
X int ret;
X
X /* Try to get MAC address from DT, or assign a random one */
X addr = of_get_mac_address(node);
X if (addr)
X ether_addr_copy(ndev->dev_addr, addr);
X else
X eth_hw_addr_random(ndev);
X
X priv->phy_node = of_parse_phandle(node, "phy", 0);
X if (!priv->phy_node) {
X netdev_err(ndev, "no associated PHY\n");
X return -ENODEV;
X }
X
X priv->phy_interface = of_get_phy_mode(node);
X if (priv->phy_interface < 0) {
X netdev_err(ndev, "PHY interface mode node unspecified\n");
X return priv->phy_interface;
X }
X
X /* Set interface mode (and configure internal PHY on H3) */
X ret = sun8i_emac_set_syscon(ndev);
X if (ret)
X return ret;
X
X ret = clk_prepare_enable(priv->ahb_clk);
X if (ret) {
X netdev_err(ndev, "Could not enable ahb clock\n");
X goto err_clk;
X }
X
X if (priv->rst) {
X ret = reset_control_deassert(priv->rst);
X if (ret) {
X netdev_err(ndev, "Could not deassert reset\n");
X goto err_reset;
X }
X }
X
X if (priv->ephy_clk) {
X ret = clk_prepare_enable(priv->ephy_clk);
X if (ret) {
X netdev_err(ndev, "Could not enable EPHY clock\n");
X goto err_ephy_clk;
X }
X }
X
X if (priv->rst_ephy) {
X ret = reset_control_deassert(priv->rst_ephy);
X if (ret) {
X netdev_err(ndev, "Could not deassert EPHY reset\n");
X goto err_ephy_reset;
X }
X }
X
X if (priv->regulator) {
X ret = regulator_enable(priv->regulator);
X if (ret)
X goto err_regulator;
X }
X
X if (priv->regulator_io) {
X ret = regulator_enable(priv->regulator_io);
X if (ret)
X goto err_regulator_io;
X }
X
X sun8i_emac_set_mdc(ndev);
X
X ret = sun8i_emac_mdio_register(ndev);
X if (ret)
X goto err_mdio_register;
X
X return 0;
X
err_mdio_register:
X if (priv->regulator_io)
X regulator_disable(priv->regulator_io);
err_regulator_io:
X if (priv->regulator)
X regulator_disable(priv->regulator);
err_regulator:
X if (priv->rst_ephy)
X reset_control_assert(priv->rst_ephy);
err_ephy_reset:
X if (priv->ephy_clk)
X clk_disable_unprepare(priv->ephy_clk);
err_ephy_clk:
X if (priv->rst)
X reset_control_assert(priv->rst);
err_reset:
X clk_disable_unprepare(priv->ahb_clk);
err_clk:
X sun8i_emac_unset_syscon(ndev);
X return ret;
}
X
static void sun8i_emac_uninit(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X
X mdiobus_unregister(priv->mdio);
X
X if (priv->regulator_io)
X regulator_disable(priv->regulator_io);
X
X if (priv->regulator)
X regulator_disable(priv->regulator);
X
X if (priv->rst_ephy)
X reset_control_assert(priv->rst_ephy);
X
X if (priv->ephy_clk)
X clk_disable_unprepare(priv->ephy_clk);
X
X if (priv->rst)
X reset_control_assert(priv->rst);
X
X clk_disable_unprepare(priv->ahb_clk);
X
X sun8i_emac_unset_syscon(ndev);
}
X
static int sun8i_emac_mdio_probe(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct phy_device *phydev = NULL;
X
X phydev = of_phy_connect(ndev, priv->phy_node, &sun8i_emac_adjust_link,
X 0, priv->phy_interface);
X
X if (!phydev) {
X netdev_err(ndev, "Could not attach to PHY\n");
X return -ENODEV;
X }
X
X phy_attached_info(phydev);
X
X /* mask with MAC supported features */
X phydev->supported &= PHY_GBIT_FEATURES;
X phydev->advertising = phydev->supported;
X
X priv->link = 0;
X priv->speed = 0;
X priv->duplex = -1;
X
X return 0;
}
X
static int sun8i_emac_open(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X int err;
X u32 v;
X struct dma_desc *ddesc;
X int i;
X
X if (nbdesc_tx < MAX_SKB_FRAGS + 1) {
X dev_err(priv->dev, "The number of TX descriptors is too low");
X return -EINVAL;
X }
X
X err = sun8i_emac_mdio_probe(ndev);
X if (err)
X return err;
X
X /* Do SOFT RST */
X v = readl(priv->base + SUN8I_EMAC_BASIC_CTL1);
X writel(v | 0x01, priv->base + SUN8I_EMAC_BASIC_CTL1);
X
X err = readl_poll_timeout(priv->base + SUN8I_EMAC_BASIC_CTL1, v,
X !(v & 0x01), 100, 10000);
X if (err) {
X dev_err(priv->dev, "EMAC reset timeout\n");
X err = -EFAULT;
X goto err_emac_timeout;
X }
X
X sun8i_emac_set_mdc(ndev);
X
X /* DMA */
X v = (8 << 24);/* burst len */
X writel(v, priv->base + SUN8I_EMAC_BASIC_CTL1);
X
X /* it seems that hardware complety ignore interrupt configuration */
#define RX_INT BIT(8)
#define TX_INT BIT(0)
#define TX_UNF_INT BIT(4)
X writel(RX_INT | TX_INT | TX_UNF_INT, priv->base + SUN8I_EMAC_INT_EN);
X
X v = readl(priv->base + SUN8I_EMAC_RX_CTL0);
X /* CHECK_CRC */
X if (ndev->features & NETIF_F_RXCSUM)
X v |= SUN8I_EMAC_RX_DO_CRC;
X else
X v &= ~SUN8I_EMAC_RX_DO_CRC;
X /* STRIP_FCS */
X if (ndev->features & NETIF_F_RXFCS)
X v &= ~SUN8I_EMAC_RX_STRIP_FCS;
X else
X v |= SUN8I_EMAC_RX_STRIP_FCS;
X writel(v, priv->base + SUN8I_EMAC_RX_CTL0);
X
X v = readl(priv->base + SUN8I_EMAC_TX_CTL1);
X /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
X v |= BIT(1);
X writel(v, priv->base + SUN8I_EMAC_TX_CTL1);
X
X v = readl(priv->base + SUN8I_EMAC_RX_CTL1);
X /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
X * complete frame has been written to RX DMA FIFO
X */
X v |= BIT(1);
X writel(v, priv->base + SUN8I_EMAC_RX_CTL1);
X
X sun8i_emac_set_macaddr(priv, ndev->dev_addr, 0);
X
X priv->tx_slot = 0;
X priv->tx_dirty = 0;
X priv->rx_dirty = 0;
X
X priv->rx_sk = kcalloc(nbdesc_rx, sizeof(struct sk_buff *), GFP_KERNEL);
X if (!priv->rx_sk) {
X err = -ENOMEM;
X goto rx_sk_error;
X }
X priv->tx_sk = kcalloc(nbdesc_tx, sizeof(struct sk_buff *), GFP_KERNEL);
X if (!priv->tx_sk) {
X err = -ENOMEM;
X goto tx_sk_error;
X }
X priv->tx_map = kcalloc(nbdesc_tx, sizeof(int), GFP_KERNEL);
X if (!priv->tx_map) {
X err = -ENOMEM;
X goto tx_map_error;
X }
X
X priv->dd_rx = dma_alloc_coherent(priv->dev,
X nbdesc_rx * sizeof(struct dma_desc),
X &priv->dd_rx_phy,
X GFP_KERNEL);
X if (!priv->dd_rx) {
X dev_err(priv->dev, "ERROR: cannot DMA RX");
X err = -ENOMEM;
X goto dma_rx_error;
X }
X memset(priv->dd_rx, 0, nbdesc_rx * sizeof(struct dma_desc));
X ddesc = priv->dd_rx;
X for (i = 0; i < nbdesc_rx; i++) {
X sun8i_emac_rx_sk(ndev, i);
X ddesc->next = (u32)priv->dd_rx_phy + (i + 1)
X * sizeof(struct dma_desc);
X ddesc++;
X }
X /* last descriptor point back to first one */
X ddesc--;
X ddesc->next = (u32)priv->dd_rx_phy;
X
X priv->dd_tx = dma_alloc_coherent(priv->dev,
X nbdesc_tx * sizeof(struct dma_desc),
X &priv->dd_tx_phy,
X GFP_KERNEL);
X if (!priv->dd_tx) {
X dev_err(priv->dev, "ERROR: cannot DMA TX");
X err = -ENOMEM;
X goto dma_tx_error;
X }
X memset(priv->dd_tx, 0, nbdesc_tx * sizeof(struct dma_desc));
X ddesc = priv->dd_tx;
X for (i = 0; i < nbdesc_tx; i++) {
X ddesc->status = DCLEAN;
X ddesc->st = 0;
X ddesc->next = (u32)(priv->dd_tx_phy + (i + 1)
X * sizeof(struct dma_desc));
X ddesc++;
X }
X /* last descriptor point back to first one */
X ddesc--;
X ddesc->next = (u32)priv->dd_tx_phy;
X i--;
X
X if (ndev->phydev)
X phy_start(ndev->phydev);
X
X /* write start of rx ring descriptor */
X writel(priv->dd_rx_phy, priv->base + SUN8I_EMAC_RX_DESC_LIST);
X /* start RX DMA */
X v = readl(priv->base + SUN8I_EMAC_RX_CTL1);
X v |= BIT(30);
X writel(v, priv->base + SUN8I_EMAC_RX_CTL1);
X
X /* write start of tx ring descriptor */
X writel(priv->dd_tx_phy, priv->base + SUN8I_EMAC_TX_DESC_LIST);
X /* start TX DMA */
X v = readl(priv->base + SUN8I_EMAC_TX_CTL1);
X v |= BIT(30);
X writel(v, priv->base + SUN8I_EMAC_TX_CTL1);
X
X /* activate transmitter */
X v = readl(priv->base + SUN8I_EMAC_TX_CTL0);
X v |= BIT(31);
X writel(v, priv->base + SUN8I_EMAC_TX_CTL0);
X
X /* activate receiver */
X v = readl(priv->base + SUN8I_EMAC_RX_CTL0);
X v |= BIT(31);
X writel(v, priv->base + SUN8I_EMAC_RX_CTL0);
X
X netif_start_queue(ndev);
X
X return 0;
dma_tx_error:
X dma_free_coherent(priv->dev, nbdesc_rx * sizeof(struct dma_desc),
X priv->dd_rx, priv->dd_rx_phy);
dma_rx_error:
X kfree(priv->tx_map);
tx_map_error:
X kfree(priv->tx_sk);
tx_sk_error:
X kfree(priv->rx_sk);
rx_sk_error:
err_emac_timeout:
X phy_disconnect(ndev->phydev);
X return err;
}
X
/* Clean the tx ring of any accepted skb for xmit */
static void sun8i_emac_tx_clean(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X int i;
X struct dma_desc *ddesc;
X int frame_len;
X
X spin_lock(&priv->tx_lock);
X
X for (i = 0; i < nbdesc_tx; i++) {
X if (priv->tx_sk[i]) {
X ddesc = priv->dd_tx + i;
X frame_len = ddesc->st & 0x3FFF;
X switch (priv->tx_map[i]) {
X case MAP_SINGLE:
X dma_unmap_single(priv->dev, ddesc->buf_addr,
X frame_len, DMA_TO_DEVICE);
X break;
X case MAP_PAGE:
X dma_unmap_page(priv->dev, ddesc->buf_addr,
X frame_len, DMA_TO_DEVICE);
X break;
X default:
X dev_err(priv->dev, "Trying to free an empty slot\n");
X continue;
X }
X dev_kfree_skb_any(priv->tx_sk[i]);
X priv->tx_sk[i] = NULL;
X ddesc->st = 0;
X ddesc->status = DCLEAN;
X }
X }
X priv->tx_slot = 0;
X priv->tx_dirty = 0;
X
X spin_unlock(&priv->tx_lock);
}
X
static int sun8i_emac_stop(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X int i;
X struct dma_desc *ddesc;
X
X /* Stop receiver */
X writel(0, priv->base + SUN8I_EMAC_RX_CTL0);
X writel(0, priv->base + SUN8I_EMAC_RX_CTL1);
X /* Stop transmitter */
X writel(0, priv->base + SUN8I_EMAC_TX_CTL0);
X writel(0, priv->base + SUN8I_EMAC_TX_CTL1);
X
X netif_stop_queue(ndev);
X netif_carrier_off(ndev);
X
X phy_stop(ndev->phydev);
X phy_disconnect(ndev->phydev);
X
X /* clean RX ring */
X for (i = 0; i < nbdesc_rx; i++)
X if (priv->rx_sk[i]) {
X ddesc = priv->dd_rx + i;
X dma_unmap_single(priv->dev, ddesc->buf_addr,
X DESC_BUF_MAX, DMA_FROM_DEVICE);
X dev_kfree_skb_any(priv->rx_sk[i]);
X priv->rx_sk[i] = NULL;
X }
X sun8i_emac_tx_clean(ndev);
X
X kfree(priv->rx_sk);
X kfree(priv->tx_sk);
X kfree(priv->tx_map);
X
X dma_free_coherent(priv->dev, nbdesc_rx * sizeof(struct dma_desc),
X priv->dd_rx, priv->dd_rx_phy);
X dma_free_coherent(priv->dev, nbdesc_tx * sizeof(struct dma_desc),
X priv->dd_tx, priv->dd_tx_phy);
X
X return 0;
}
X
static netdev_tx_t sun8i_emac_xmit(struct sk_buff *skb, struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct dma_desc *ddesc;
X struct dma_desc *first;
X int i = 0, rbd_first;
X unsigned int len, fraglen;
X u32 v;
X int n;
X int nf;
X const skb_frag_t *frag;
X int do_csum = 0;
X
X len = skb_headlen(skb);
X if (len < ETH_ZLEN) {
X if (skb_padto(skb, ETH_ZLEN))
X return NETDEV_TX_OK;
X len = ETH_ZLEN;
X }
X n = skb_shinfo(skb)->nr_frags;
X
X if (skb->ip_summed == CHECKSUM_PARTIAL) {
X do_csum = 1;
X priv->estats.tx_hw_csum++;
X }
X netif_dbg(priv, tx_queued, ndev, "%s len=%u skblen=%u %x\n", __func__,
X len, skb->len,
X (skb->ip_summed == CHECKSUM_PARTIAL));
X
X spin_lock(&priv->tx_lock);
X
X /* check for contigous space
X * We need at least 1(skb->data) + n(numfrags) + 1(one clean slot)
X */
X if (rb_tx_numfreedesc(ndev) < n + 2) {
X dev_err_ratelimited(priv->dev, "BUG!: TX is full %d %d\n",
X priv->tx_dirty, priv->tx_slot);
X netif_stop_queue(ndev);
X spin_unlock(&priv->tx_lock);
X return NETDEV_TX_BUSY;
X }
X i = priv->tx_slot;
X
X ddesc = priv->dd_tx + i;
X first = priv->dd_tx + i;
X rbd_first = i;
X
X priv->tx_slot = (i + 1 + n) % nbdesc_tx;
X
X ddesc->buf_addr = dma_map_single(priv->dev, skb->data, len,
X DMA_TO_DEVICE);
X if (dma_mapping_error(priv->dev, ddesc->buf_addr)) {
X dev_err(priv->dev, "ERROR: Cannot dmamap buf\n");
X goto xmit_error;
X }
X priv->tx_map[i] = MAP_SINGLE;
X priv->tx_sk[i] = skb;
X priv->ndev->stats.tx_packets++;
X priv->ndev->stats.tx_bytes += len;
X
X ddesc->st = len;
X /* undocumented bit that make it works */
X ddesc->st |= BIT(24);
X if (do_csum)
X ddesc->st |= SUN8I_EMAC_TX_DO_CRC;
X
X /* handle fragmented skb, one descriptor per fragment */
X for (nf = 0; nf < n; nf++) {
X frag = &skb_shinfo(skb)->frags[nf];
X rb_inc(&i, nbdesc_tx);
X priv->tx_sk[i] = skb;
X ddesc = priv->dd_tx + i;
X fraglen = skb_frag_size(frag);
X ddesc->st = fraglen;
X priv->ndev->stats.tx_bytes += fraglen;
X ddesc->st |= BIT(24);
X if (do_csum)
X ddesc->st |= SUN8I_EMAC_TX_DO_CRC;
X
X ddesc->buf_addr = skb_frag_dma_map(priv->dev, frag, 0,
X fraglen, DMA_TO_DEVICE);
X if (dma_mapping_error(priv->dev, ddesc->buf_addr)) {
X dev_err(priv->dev, "DMA MAP ERROR\n");
X goto xmit_error;
X }
X priv->tx_map[i] = MAP_PAGE;
X ddesc->status = BIT(31);
X }
X
X /* frame end */
X ddesc->st |= BIT(30);
X /* We want an interrupt after transmission */
X ddesc->st |= BIT(31);
X
X rb_inc(&i, nbdesc_tx);
X
X /* frame begin */
X first->st |= BIT(29);
X first->status = BIT(31);
X priv->tx_slot = i;
X
X /* Trying to optimize this (recording DMA start/stop) seems
X * to lead to errors. So we always start DMA.
X */
X v = readl(priv->base + SUN8I_EMAC_TX_CTL1);
X /* TX DMA START */
X v |= BIT(31);
X /* Start an run DMA */
X v |= BIT(30);
X writel(v, priv->base + SUN8I_EMAC_TX_CTL1);
X
X if (rb_tx_numfreedesc(ndev) < MAX_SKB_FRAGS + 1) {
X netif_stop_queue(ndev);
X priv->estats.tx_stop_queue++;
X }
X priv->estats.tx_used_desc = rb_tx_numfreedesc(ndev);
X
X spin_unlock(&priv->tx_lock);
X
X return NETDEV_TX_OK;
X
xmit_error:
X /* destroy skb and return TX OK Documentation/DMA-API-HOWTO.txt */
X /* clean descritors from rbd_first to i */
X ddesc->st = 0;
X ddesc->status = DCLEAN;
X do {
X ddesc = priv->dd_tx + rbd_first;
X ddesc->st = 0;
X ddesc->status = DCLEAN;
X rb_inc(&rbd_first, nbdesc_tx);
X } while (rbd_first != i);
X spin_unlock(&priv->tx_lock);
X dev_kfree_skb_any(skb);
X return NETDEV_TX_OK;
}
X
static int sun8i_emac_change_mtu(struct net_device *ndev, int new_mtu)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X int max_mtu;
X
X dev_info(priv->dev, "%s set MTU to %d\n", __func__, new_mtu);
X
X if (netif_running(ndev)) {
X dev_err(priv->dev, "%s: must be stopped to change its MTU\n",
X ndev->name);
X return -EBUSY;
X }
X
X max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
X
X if ((new_mtu < 68) || (new_mtu > max_mtu)) {
X dev_err(priv->dev, "%s: invalid MTU, max MTU is: %d\n",
X ndev->name, max_mtu);
X return -EINVAL;
X }
X
X ndev->mtu = new_mtu;
X netdev_update_features(ndev);
X return 0;
}
X
static netdev_features_t sun8i_emac_fix_features(struct net_device *ndev,
X netdev_features_t features)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X
X netif_dbg(priv, drv, ndev, "%s %llx\n", __func__, features);
X return features;
}
X
static int sun8i_emac_set_features(struct net_device *ndev,
X netdev_features_t features)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X u32 v;
X
X v = readl(priv->base + SUN8I_EMAC_BASIC_CTL0);
X if (features & NETIF_F_LOOPBACK && netif_running(ndev)) {
X netif_info(priv, hw, ndev, "Set loopback features");
X v |= BIT(1);
X } else {
X netif_info(priv, hw, ndev, "Unset loopback features");
X v &= ~BIT(1);
X }
X writel(v, priv->base + SUN8I_EMAC_BASIC_CTL0);
X
X v = readl(priv->base + SUN8I_EMAC_RX_CTL0);
X if (features & NETIF_F_RXCSUM) {
X v |= SUN8I_EMAC_RX_DO_CRC;
X netif_info(priv, hw, ndev, "Doing RX CRC check by hardware");
X } else {
X v &= ~SUN8I_EMAC_RX_DO_CRC;
X netif_info(priv, hw, ndev, "No RX CRC check by hardware");
X }
X if (features & NETIF_F_RXFCS) {
X v &= ~SUN8I_EMAC_RX_STRIP_FCS;
X netif_info(priv, hw, ndev, "Keep FCS");
X } else {
X v |= SUN8I_EMAC_RX_STRIP_FCS;
X netif_info(priv, hw, ndev, "Strip FCS");
X }
X writel(v, priv->base + SUN8I_EMAC_RX_CTL0);
X
X netif_dbg(priv, drv, ndev, "%s %llx %x\n", __func__, features, v);
X
X return 0;
}
X
static void sun8i_emac_set_rx_mode(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X u32 v = 0;
X int i = 0;
X struct netdev_hw_addr *ha;
X
X /* Receive all multicast frames */
X v |= BIT(16);
X /* Receive all control frames */
X v |= BIT(13);
X if (ndev->flags & IFF_PROMISC)
X v |= BIT(1);
X if (netdev_uc_count(ndev) > 7) {
X v |= BIT(1);
X } else {
X netdev_for_each_uc_addr(ha, ndev) {
X i++;
X sun8i_emac_set_macaddr(priv, ha->addr, i);
X }
X }
X writel(v, priv->base + SUN8I_EMAC_RX_FRM_FLT);
}
X
static void sun8i_emac_tx_timeout(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X u32 v;
X
X dev_info(priv->dev, "%s\n", __func__);
X netif_stop_queue(ndev);
X
X v = readl(priv->base + SUN8I_EMAC_TX_CTL0);
X v &= ~BIT(31);
X writel(v, priv->base + SUN8I_EMAC_TX_CTL0);
X
X v = readl(priv->base + SUN8I_EMAC_TX_CTL1);
X v &= ~BIT(31);
X v &= ~BIT(30);
X writel(v, priv->base + SUN8I_EMAC_TX_CTL1);
X
X sun8i_emac_tx_clean(ndev);
X
X /* write start of tx ring descriptor */
X writel(priv->dd_tx_phy, priv->base + SUN8I_EMAC_TX_DESC_LIST);
X
X v = readl(priv->base + SUN8I_EMAC_TX_CTL0);
X v |= BIT(31);
X writel(v, priv->base + SUN8I_EMAC_TX_CTL0);
X
X v = readl(priv->base + SUN8I_EMAC_TX_CTL1);
X v |= BIT(31);
X v |= BIT(30);
X writel(v, priv->base + SUN8I_EMAC_TX_CTL1);
X
X netdev_reset_queue(ndev);
X
X ndev->stats.tx_errors++;
X netif_wake_queue(ndev);
}
X
static int sun8i_emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
{
X struct phy_device *phydev = ndev->phydev;
X
X if (!netif_running(ndev))
X return -EINVAL;
X
X if (!phydev)
X return -ENODEV;
X
X return phy_mii_ioctl(phydev, rq, cmd);
}
X
static int sun8i_emac_check_if_running(struct net_device *ndev)
{
X if (!netif_running(ndev))
X return -EBUSY;
X return 0;
}
X
static int sun8i_emac_get_sset_count(struct net_device *ndev, int sset)
{
X switch (sset) {
X case ETH_SS_STATS:
X return ARRAY_SIZE(estats_str);
X }
X return -EOPNOTSUPP;
}
X
static int sun8i_emac_ethtool_get_settings(struct net_device *ndev,
X struct ethtool_cmd *cmd)
{
X struct phy_device *phy = ndev->phydev;
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X
X if (!phy) {
X netdev_err(ndev, "%s: %s: PHY is not registered\n",
X __func__, ndev->name);
X return -ENODEV;
X }
X
X if (!netif_running(ndev)) {
X dev_err(priv->dev, "interface disabled: we cannot track link speed / duplex setting\n");
X return -EBUSY;
X }
X
X cmd->transceiver = XCVR_INTERNAL;
X return phy_ethtool_gset(phy, cmd);
}
X
static int sun8i_emac_ethtool_set_settings(struct net_device *ndev,
X struct ethtool_cmd *cmd)
{
X struct phy_device *phy = ndev->phydev;
X
X return phy_ethtool_sset(phy, cmd);
}
X
static void sun8i_emac_ethtool_getdrvinfo(struct net_device *ndev,
X struct ethtool_drvinfo *info)
{
X strlcpy(info->driver, "sun8i_emac", sizeof(info->driver));
X strcpy(info->version, "00");
X info->fw_version[0] = '\0';
}
X
static void sun8i_emac_ethtool_stats(struct net_device *ndev,
X struct ethtool_stats *dummy, u64 *data)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X
X memcpy(data, &priv->estats,
X sun8i_emac_get_sset_count(ndev, ETH_SS_STATS) * sizeof(u64));
}
X
static void sun8i_emac_ethtool_strings(struct net_device *dev, u32 stringset,
X u8 *buffer)
{
X switch (stringset) {
X case ETH_SS_STATS:
X memcpy(buffer, &estats_str,
X sun8i_emac_get_sset_count(dev, ETH_SS_STATS) *
X sizeof(struct ethtool_str));
X break;
X }
}
X
static u32 sun8i_emac_ethtool_getmsglevel(struct net_device *ndev)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X
X return priv->msg_enable;
}
X
static void sun8i_emac_ethtool_setmsglevel(struct net_device *ndev, u32 level)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X
X priv->msg_enable = level;
}
X
static void sun8i_emac_get_pauseparam(struct net_device *ndev,
X struct ethtool_pauseparam *pause)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X
X pause->rx_pause = 0;
X pause->tx_pause = 0;
X pause->autoneg = ndev->phydev->autoneg;
X
X if (priv->flow_ctrl & FLOW_RX)
X pause->rx_pause = 1;
X if (priv->flow_ctrl & FLOW_TX)
X pause->tx_pause = 1;
}
X
static int sun8i_emac_set_pauseparam(struct net_device *ndev,
X struct ethtool_pauseparam *pause)
{
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X struct phy_device *phy = ndev->phydev;
X int new_pause = 0;
X int ret = 0;
X
X if (pause->rx_pause)
X new_pause |= FLOW_RX;
X if (pause->tx_pause)
X new_pause |= FLOW_TX;
X
X priv->flow_ctrl = new_pause;
X phy->autoneg = pause->autoneg;
X
X if (phy->autoneg) {
X if (netif_running(ndev))
X ret = phy_start_aneg(phy);
X } else {
X sun8i_emac_flow_ctrl(priv, phy->duplex, priv->flow_ctrl,
X priv->pause);
X }
X return ret;
}
X
static const struct ethtool_ops sun8i_emac_ethtool_ops = {
X .begin = sun8i_emac_check_if_running,
X .get_settings = sun8i_emac_ethtool_get_settings,
X .set_settings = sun8i_emac_ethtool_set_settings,
X .get_link = ethtool_op_get_link,
X .get_pauseparam = sun8i_emac_get_pauseparam,
X .set_pauseparam = sun8i_emac_set_pauseparam,
X .get_ethtool_stats = sun8i_emac_ethtool_stats,
X .get_strings = sun8i_emac_ethtool_strings,
X .get_wol = NULL,
X .set_wol = NULL,
X .get_sset_count = sun8i_emac_get_sset_count,
X .get_drvinfo = sun8i_emac_ethtool_getdrvinfo,
X .get_msglevel = sun8i_emac_ethtool_getmsglevel,
X .set_msglevel = sun8i_emac_ethtool_setmsglevel,
};
X
static const struct net_device_ops sun8i_emac_netdev_ops = {
X .ndo_init = sun8i_emac_init,
X .ndo_uninit = sun8i_emac_uninit,
X .ndo_open = sun8i_emac_open,
X .ndo_start_xmit = sun8i_emac_xmit,
X .ndo_stop = sun8i_emac_stop,
X .ndo_change_mtu = sun8i_emac_change_mtu,
X .ndo_fix_features = sun8i_emac_fix_features,
X .ndo_set_rx_mode = sun8i_emac_set_rx_mode,
X .ndo_tx_timeout = sun8i_emac_tx_timeout,
X .ndo_do_ioctl = sun8i_emac_ioctl,
X .ndo_set_mac_address = eth_mac_addr,
X .ndo_set_features = sun8i_emac_set_features,
};
X
static irqreturn_t sun8i_emac_dma_interrupt(int irq, void *dev_id)
{
X struct net_device *ndev = (struct net_device *)dev_id;
X struct sun8i_emac_priv *priv = netdev_priv(ndev);
X u32 v, u;
X
X v = readl(priv->base + SUN8I_EMAC_INT_STA);
X
X netif_info(priv, intr, ndev, "%s %x\n", __func__, v);
X
X /* When this bit is asserted, a frame transmission is completed. */
X if (v & BIT(0))
X sun8i_emac_complete_xmit(ndev);
X
X /* When this bit is asserted, the TX DMA FSM is stopped. */
X if (v & BIT(1))
X priv->estats.tx_dma_stop++;
X
X /* When this asserted, the TX DMA can not acquire next TX descriptor
X * and TX DMA FSM is suspended.
X */
X if (v & BIT(2))
X priv->estats.tx_dma_ua++;
X
X if (v & BIT(3))
X netif_dbg(priv, intr, ndev, "Unhandled interrupt TX TIMEOUT\n");
X
X if (v & BIT(4)) {
X netif_dbg(priv, intr, ndev, "Unhandled interrupt TX underflow\n");
X priv->estats.tx_underflow_int++;
X }
X
X /* When this bit asserted , the frame is transmitted to FIFO totally. */
X if (v & BIT(5)) {
X netif_dbg(priv, intr, ndev, "Unhandled interrupt TX_EARLY_INT\n");
X priv->estats.tx_early_int++;
X }
X
X /* When this bit is asserted, a frame reception is completed */
X if (v & BIT(8))
X sun8i_emac_receive_all(ndev);
X
X /* When this asserted, the RX DMA can not acquire next TX descriptor
X * and RX DMA FSM is suspended.
X */
X if (v & BIT(9)) {
X u = readl(priv->base + SUN8I_EMAC_RX_CTL1);
X dev_info(priv->dev, "Re-run RX DMA %x\n", u);
X writel(u | BIT(31), priv->base + SUN8I_EMAC_RX_CTL1);
X priv->estats.rx_dma_ua++;
X }
X
X if (v & BIT(10)) {
X netif_dbg(priv, intr, ndev, "Unhandled interrupt RX_DMA_STOPPED_INT\n");
X priv->estats.rx_dma_stop++;
X }
X if (v & BIT(11))
X netif_dbg(priv, intr, ndev, "Unhandled interrupt RX_TIMEOUT\n");
X if (v & BIT(12))
X netif_dbg(priv, intr, ndev, "Unhandled interrupt RX OVERFLOW\n");
X if (v & BIT(13)) {
X netif_dbg(priv, intr, ndev, "Unhandled interrupt RX EARLY\n");
X priv->estats.rx_early_int++;
X }
X if (v & BIT(16))
X netif_dbg(priv, intr, ndev, "Unhandled interrupt RGMII\n");
X
X /* the datasheet state those register as read-only
X * but nothing work without writing to it
X */
X writel(v & 0x3FFF, priv->base + SUN8I_EMAC_INT_STA);
X
X return IRQ_HANDLED;
}
X
static int sun8i_emac_probe(struct platform_device *pdev)
{
X struct resource *res;
X struct device_node *np = pdev->dev.of_node;
X struct sun8i_emac_priv *priv;
X struct net_device *ndev;
X int ret;
X
X ndev = alloc_etherdev(sizeof(*priv));
X if (!ndev)
X return -ENOMEM;
X
X SET_NETDEV_DEV(ndev, &pdev->dev);
X priv = netdev_priv(ndev);
X platform_set_drvdata(pdev, ndev);
X
X priv->variant = (enum emac_variant)of_device_get_match_data(&pdev->dev);
X
X res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
X priv->base = devm_ioremap_resource(&pdev->dev, res);
X if (IS_ERR(priv->base)) {
X ret = PTR_ERR(priv->base);
X dev_err(&pdev->dev, "Cannot request MMIO: %d\n", ret);
X goto probe_err;
X }
X
X res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscon");
X priv->syscon = devm_ioremap_resource(&pdev->dev, res);
X if (IS_ERR(priv->syscon)) {
X ret = PTR_ERR(priv->syscon);
X dev_err(&pdev->dev,
X "Cannot map system control registers: %d\n", ret);
X goto probe_err;
X }
X
X priv->irq = platform_get_irq(pdev, 0);
X if (priv->irq < 0) {
X ret = priv->irq;
X dev_err(&pdev->dev, "Cannot claim IRQ: %d\n", ret);
X goto probe_err;
X }
X
X ret = devm_request_irq(&pdev->dev, priv->irq, sun8i_emac_dma_interrupt,
X 0, dev_name(&pdev->dev), ndev);
X if (ret) {
X dev_err(&pdev->dev, "Cannot request IRQ: %d\n", ret);
X goto probe_err;
X }
X
X priv->ahb_clk = devm_clk_get(&pdev->dev, "ahb");
X if (IS_ERR(priv->ahb_clk)) {
X ret = PTR_ERR(priv->ahb_clk);
X dev_err(&pdev->dev, "Cannot get AHB clock err=%d\n", ret);
X goto probe_err;
X }
X
X priv->rst = devm_reset_control_get_optional(&pdev->dev, "ahb");
X if (IS_ERR(priv->rst)) {
X ret = PTR_ERR(priv->rst);
X if (ret == -EPROBE_DEFER)
X return -EPROBE_DEFER;
X dev_info(&pdev->dev, "no mac reset control found %d\n", ret);
X priv->rst = NULL;
X }
X
X if (priv->variant == H3_EMAC)
X priv->use_internal_phy =
X of_property_read_bool(np, "allwinner,use-internal-phy");
X
X if (priv->use_internal_phy) {
X priv->ephy_clk = devm_clk_get(&pdev->dev, "ephy");
X if (IS_ERR(priv->ephy_clk)) {
X ret = PTR_ERR(priv->ephy_clk);
X dev_err(&pdev->dev, "Cannot get EPHY clock err=%d\n",
X ret);
X goto probe_err;
X }
X
X priv->rst_ephy = devm_reset_control_get_optional(&pdev->dev,
X "ephy");
X if (IS_ERR(priv->rst_ephy)) {
X ret = PTR_ERR(priv->rst_ephy);
X if (ret == -EPROBE_DEFER)
X goto probe_err;
X dev_info(&pdev->dev,
X "no EPHY reset control found %d\n", ret);
X priv->rst_ephy = NULL;
X }
X }
X
X /* Optional regulator for PHY */
X priv->regulator = devm_regulator_get_optional(&pdev->dev, "phy");
X if (IS_ERR(priv->regulator)) {
X if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
X ret = -EPROBE_DEFER;
X goto probe_err;
X }
X dev_dbg(&pdev->dev, "no PHY regulator found\n");
X priv->regulator = NULL;
X } else {
X dev_info(&pdev->dev, "PHY regulator found\n");
X }
X
X /* Optional regulator for PHY I/O */
X priv->regulator_io = devm_regulator_get_optional(&pdev->dev, "phy_io");
X if (IS_ERR(priv->regulator_io)) {
X if (PTR_ERR(priv->regulator_io) == -EPROBE_DEFER) {
X ret = -EPROBE_DEFER;
X goto probe_err;
X }
X dev_dbg(&pdev->dev, "no PHY I/O regulator found\n");
X priv->regulator_io = NULL;
X } else {
X dev_info(&pdev->dev, "PHY IO regulator found\n");
X }
X
X spin_lock_init(&priv->lock);
X spin_lock_init(&priv->tx_lock);
X
X ndev->netdev_ops = &sun8i_emac_netdev_ops;
X ndev->ethtool_ops = &sun8i_emac_ethtool_ops;
X
X priv->ndev = ndev;
X priv->dev = &pdev->dev;
X
X ndev->base_addr = (unsigned long)priv->base;
X ndev->irq = priv->irq;
X
X ndev->hw_features = NETIF_F_SG | NETIF_F_HIGHDMA;
X ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
X NETIF_F_RXCSUM;
X ndev->features |= ndev->hw_features;
X ndev->hw_features |= NETIF_F_RXFCS;
X ndev->hw_features |= NETIF_F_RXALL;
X ndev->hw_features |= NETIF_F_LOOPBACK;
X ndev->priv_flags |= IFF_UNICAST_FLT;
X
X ndev->watchdog_timeo = msecs_to_jiffies(5000);
X
X ret = register_netdev(ndev);
X if (ret) {
X dev_err(&pdev->dev, "ERROR: Register %s failed\n", ndev->name);
X goto probe_err;
X }
X
X return 0;
X
probe_err:
X free_netdev(ndev);
X return ret;
}
X
static int sun8i_emac_remove(struct platform_device *pdev)
{
X struct net_device *ndev = platform_get_drvdata(pdev);
X
X unregister_netdev(ndev);
X platform_set_drvdata(pdev, NULL);
X free_netdev(ndev);
X
X return 0;
}
X
static const struct of_device_id sun8i_emac_of_match_table[] = {
X { .compatible = "allwinner,sun8i-a83t-emac",
X .data = (void *)A83T_EMAC },
X { .compatible = "allwinner,sun8i-h3-emac",
X .data = (void *)H3_EMAC },
X { .compatible = "allwinner,sun50i-a64-emac",
X .data = (void *)A64_EMAC },
X {}
};
MODULE_DEVICE_TABLE(of, sun8i_emac_of_match_table);
X
static struct platform_driver sun8i_emac_driver = {
X .probe = sun8i_emac_probe,
X .remove = sun8i_emac_remove,
X .driver = {
X .name = "sun8i-emac",
X .of_match_table = sun8i_emac_of_match_table,
X },
};
X
module_platform_driver(sun8i_emac_driver);
X
MODULE_DESCRIPTION("sun8i Ethernet driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("LABBE Corentin <clabbe....@gmail.com");
SHAR_EOF
(set 20 16 12 09 23 58 27 'sun8i/sun8i-emac.c'
eval "${shar_touch}") && \
chmod 0644 'sun8i/sun8i-emac.c'
if test $? -ne 0
then ${echo} "restore of sun8i/sun8i-emac.c failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'sun8i/sun8i-emac.c': 'MD5 check failed'
) << \SHAR_EOF
9c6d3a98818db2f65f6ed629fc50f877 sun8i/sun8i-emac.c
SHAR_EOF

else
test `LC_ALL=C wc -c < 'sun8i/sun8i-emac.c'` -ne 49859 && \
${echo} "restoration warning: size of 'sun8i/sun8i-emac.c' is not 49859"
fi
fi
# ============= buildroot-2016.11/package/sun8i-emac-module/Config.in ==============
if test ! -d 'buildroot-2016.11'; then
mkdir 'buildroot-2016.11'
if test $? -eq 0
then ${echo} "x - created directory buildroot-2016.11."
else ${echo} "x - failed to create directory buildroot-2016.11."
exit 1
fi
fi
if test ! -d 'buildroot-2016.11/package'; then
mkdir 'buildroot-2016.11/package'
if test $? -eq 0
then ${echo} "x - created directory buildroot-2016.11/package."
else ${echo} "x - failed to create directory buildroot-2016.11/package."
exit 1
fi
fi
if test ! -d 'buildroot-2016.11/package/sun8i-emac-module'; then
mkdir 'buildroot-2016.11/package/sun8i-emac-module'
if test $? -eq 0
then ${echo} "x - created directory buildroot-2016.11/package/sun8i-emac-module."
else ${echo} "x - failed to create directory buildroot-2016.11/package/sun8i-emac-module."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'buildroot-2016.11/package/sun8i-emac-module/Config.in'
then
${echo} "x - SKIPPING buildroot-2016.11/package/sun8i-emac-module/Config.in (file already exists)"

else
${echo} "x - extracting buildroot-2016.11/package/sun8i-emac-module/Config.in (text)"
sed 's/^X//' << 'SHAR_EOF' > 'buildroot-2016.11/package/sun8i-emac-module/Config.in' &&
config BR2_PACKAGE_SUN8I_EMAC_MODULE
X bool "sun8i-emac-module"
X depends on BR2_LINUX_KERNEL
X help
X Driver for Ethernet in H3 bridge.
X
X https://github.com/montjoie/linux/blob/sun8i-emac-wip/drivers/net/ethernet/allwinner/sun8i-emac.c
X
comment "sun8i-emac-module needs a Linux kernel to be built"
X depends on !BR2_LINUX_KERNEL
SHAR_EOF
(set 20 16 12 10 00 44 37 'buildroot-2016.11/package/sun8i-emac-module/Config.in'
eval "${shar_touch}") && \
chmod 0644 'buildroot-2016.11/package/sun8i-emac-module/Config.in'
if test $? -ne 0
then ${echo} "restore of buildroot-2016.11/package/sun8i-emac-module/Config.in failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'buildroot-2016.11/package/sun8i-emac-module/Config.in': 'MD5 check failed'
) << \SHAR_EOF
d80df9e39ccd94fe3dd70f6664bbdc0a buildroot-2016.11/package/sun8i-emac-module/Config.in
SHAR_EOF

else
test `LC_ALL=C wc -c < 'buildroot-2016.11/package/sun8i-emac-module/Config.in'` -ne 336 && \
${echo} "restoration warning: size of 'buildroot-2016.11/package/sun8i-emac-module/Config.in' is not 336"
fi
fi
# ============= buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk ==============
if test ! -d 'buildroot-2016.11/package/sun8i-emac-module'; then
mkdir 'buildroot-2016.11/package/sun8i-emac-module'
if test $? -eq 0
then ${echo} "x - created directory buildroot-2016.11/package/sun8i-emac-module."
else ${echo} "x - failed to create directory buildroot-2016.11/package/sun8i-emac-module."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk'
then
${echo} "x - SKIPPING buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk (file already exists)"

else
${echo} "x - extracting buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk (text)"
sed 's/^X//' << 'SHAR_EOF' > 'buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk' &&
################################################################################
#
# SUN8I_EMAC-module
#
################################################################################
X
SUN8I_EMAC_MODULE_VERSION = 1.0
SUN8I_EMAC_MODULE_SITE = $(TOPDIR)/../sun8i
SUN8I_EMAC_MODULE_SITE_METHOD = local
SUN8I_EMAC_MODULES_LICENSE = LGPLv2.1/GPLv2
X
SUN8I_EMAC_MODULE_DEPENDENCIES = linux
X
define SUN8I_EMAC_MODULE_BUILD_CMDS
X $(MAKE) -C $(@D) $(LINUX_MAKE_FLAGS) KERNELDIR=$(LINUX_DIR)
endef
X
define SUN8I_EMAC_MODULE_INSTALL_TARGET_CMDS
X $(MAKE) -C $(@D) $(LINUX_MAKE_FLAGS) KERNELDIR=$(LINUX_DIR) modules_install
endef
X
$(eval $(generic-package))
SHAR_EOF
(set 20 16 12 10 00 23 17 'buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk'
eval "${shar_touch}") && \
chmod 0644 'buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk'
if test $? -ne 0
then ${echo} "restore of buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk': 'MD5 check failed'
) << \SHAR_EOF
575bfa239ba5dfe2947cb0934d54fa45 buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk
SHAR_EOF

else
test `LC_ALL=C wc -c < 'buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk'` -ne 651 && \
${echo} "restoration warning: size of 'buildroot-2016.11/package/sun8i-emac-module/sun8i-emac-module.mk' is not 651"
fi
fi
if rm -fr ${lock_dir}
then ${echo} "x - removed lock directory ${lock_dir}."
else ${echo} "x - failed to remove lock directory ${lock_dir}."
exit 1
fi
exit 0

wza...@gmail.com

unread,
Dec 16, 2016, 10:19:21 AM12/16/16
to
There is one thing lacking in the description. If you compile using the Buildroot toolchain, you'll get problems with version of kernel headers.

Therefore the right procedure is:
1. Download Buildroot ( https://buildroot.org/downloads/buildroot-2016.11.tar.bz2 ) and unpack it.
2. In the same directory extract the previous post (if you access it via Google archive, remember to store it in "original" form).
3. In the buildroot-2016.11 directory run "make orangepipc_defconfig"
4. You should manually modify the package/Config.in file, adding the reference
to the new package:
source "package/sun8i-emac-module/Config.in"
To add it in a chosen position in "Target packages" section.
5. Unpack the previous post in the directory ABOVE the "buildroot-2016.11" directory with "unshar -f file_with_saved_post"
6. In the buildroot-2016.11 directory, run "make menuconfig" and:
a. In section "Kernel/Custom kernel patches" set (../kernel_patches)
b. In section "Target packages" select the "sun8i-emac-module"
c. In section "Kernel/Kernel version" change (4.7.3) to (4.9)
d. Toolchain/"Toolchain type" set to (External toolchain)
in my case it automatically selects the "Linaro ARM 2016.05"
e. Introduce any other desired configuration changes (select target packages etc.)

After you exit the menuconfig, you may run "make" to build your image

paa123456

unread,
Jan 6, 2017, 3:12:47 PM1/6/17
to
Hello Wojtek,

I have been following the steps that you outline.

I did build a minimal image for orange-pi-pc using the original buidroot _defconfig .
I am using the 'ubuntu' utility 'disk image writer' to put the image on a sd card.
The image creates 2 partitions - 10mb fat, and around 500mb ext4.

The problem is the image does not boot - nothing comes on screen.
What could be the problem? Are there additional steps after putting the image on a sd card?

According to your post the image made by default opi-pc buildroot config file has 4.7 kernel and boots ok.
In order to get ethernet working , you edit the buildroot .config - switch to plain 4.9 kernel, and use linaro compiler, instead of the the standard gnu one.
I can try these steps as well.

Best regards,
Paul.

wza...@gmail.com

unread,
Mar 30, 2017, 6:13:17 PM3/30/17
to
Dear Paul,
What do you use as a "screen"? I'm using OrangePiPC as an embedded system, so my "Screen" is the serial console, connected via USB/UART converter.
It is not an HDMI display!

Best regards,
Wojtek
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