DEC Technology
John C Slimick
To (hopefully) clarify the discussion of DEC Technology
in early times, let me add the following:
The PDP was built of large boards, all in the 4 digit series:
I believe that the 4705/4706 were the serial transmitter/
receiver boards. Some boards seemed to have nothing but copper
on them, with a small number of discretes; these, I was told,
used the trace lengths as necessary delays, and were known as
"bedsheet" boards.
DEC in the mid-60's had a line of modules that were, as I recall,
about 4" by 6". There were three main lines, all indicated by
the color of the identifier tab on the end away from the pins that
would feed into the bus:
R (Red) series -- 2 Mghz
B (Blue) series -- 10 Mghz
W (White) series -- I/O
All used a negative logic (-3v = 1 and gnd = 0) and all used
discretes in a technology known as DCD (diode-capacitor-diode).
Examples:
R113 Five 2-input NAND/NOR $20.00
R201 Flip-Flop $22.00
B201 Flip-Flop $56.00
W706 Teletype Receiver $150.00
(double size)
(All of these are from my 67 Logic Handbook -- you still have
your copy don't you? One of the appealing things about DEC
was that they wanted you to use their modules and to understand
how their logic worked, so you would buy more)
In 68 or 69 DEC introduced their M (Magenta) series which featured
SSI devices on a standard module card. I believe that the PDP 9I
was built (mostly) of such modules and was DEC's first IC machine.
There was also a cost reduced version of the 9, the 9L, which may
may have been an IC machine.
Talk about split personalities: all of the 8's up to the 8A were
negative bus machines (where you clipped diodes from a W103 to
perform device selection), but with the 8A came the omnibus(tm)
positive bus machine.
Opinion: I remember DEC when it was engineering oriented...
john slimick
sli...@unix.cis.pitt.edu
university of pittsburgh at bradford
Phil Gustafson
>
>DEC in the mid-60's had a line of modules that were, as I recall,
>about 4" by 6". There were three main lines, all indicated by
>the color of the identifier tab on the end away from the pins that
>would feed into the bus:
>
> R (Red) series -- 2 Mghz
> B (Blue) series -- 10 Mghz
> W (White) series -- I/O
>
I'm looking at a rather dusty B611 dual pulse driver right now. It's
2.5" x 5", including all 18 contact pins, but not its blue handle. It
holds two two-input gates, two clamped loads, and two pulse drivers. It's
not particularly crowded, but when you add a safety ground or two all the
pins are used up.
The pulse formers are kinda neat. Each uses a pair of transformers made
of ferrite torii, each with a couple windings and each protected by a
hemishpherical blob of a hard orange something. The output windings go
directly to output pins. Fire the inverter driving the transformer and
the output makes a standard 30-nS (I think) pulse. By different connections
of the outputs you can make pulses of either sex.
>All used a negative logic (-3v = 1 and gnd = 0) and all used
>discretes in a technology known as DCD (diode-capacitor-diode).
Each flip-chip had its own on-board regulated supply to derive -3V from
the -15V supply. The supply was a resistor sending current thru four
diodes in series. By the time you added a clamp diode to the outside
world, the logic level was -3V. In fact, the two basic kinds of diodes
on the boards are "switching diodes" and "dropping diodes", the latter
of which was never biased backwards. One artifact of this design was
the chips' ability to operate over a wide range of input voltages, but
hopefully someone else will talk about "margins". (On this board the
power-supply resistor is made of (squint) three 750-ohm and three
810-ohm resistors in parallel. It was cheaper to use the automatic
component-stuffers six time than to install one or two higher-dissipation
resistors by hand.)
The logic was called, I believe, LLL (low-level logic), sort of a gainless
cousin of TTL. A diode gate fed the inverter base through a pair of
dropping diodes to improve noise resistance.
>Examples:
The B212 flip-flop used on the PDP-10. Each flip-flop had a little pair
of delay lines on the inputs, just like the ones in the textbooks.
>In 68 or 69 DEC introduced their M (Magenta) series which featured
>SSI devices on a standard module card. I believe that the PDP 9I
>was built (mostly) of such modules and was DEC's first IC machine.
Either that or the 8I. Anyhow, the 8, 9, and 10 each initially used
discrete components. I believe that the only IC's in the KA-10 were
in the console TTY controller and the optional fast accumulators.
>john slimick
phil gustafson
--
| ph...@zorch.SF-Bay.ORG | Phil Gustafson
| {ames|pyramid|vsi1}!zorch!phil | UN*X/graphics consultant
| sgi!gsi!phil | 1550 Martin Ave., San Jose CA 95126
| phil@gsi | 408/286-1749
Phil Gustafson
>The logic was called, I believe, LLL (low-level logic), sort of a gainless
>cousin of TTL.
As often happens, I misspeak when I try to be clever. Obviously, the
inverter has gain. There's just no gain in the input stage.
phil
Bob Clements
A few comments and corrections to two articles:
<118...@unix.cis.pitt.edu> by sli...@unix.cis.pitt.edu (John C Slimick) and
<1991Apr23.0...@zorch.SF-Bay.ORG>
by ph...@zorch.SF-Bay.ORG (Phil Gustafson):
In article <118...@unix.cis.pitt.edu> sli...@unix.cis.pitt.edu (John C Slimick) writes:
>
>jcs> The PDP was built of large boards, all in the 4 digit series:
^^^^^^^
A typo, I guess, since not all "PDP-n" machines were built out of
the same technology of boards.
>jcs> R (Red) series -- 2 Mghz
>jcs> B (Blue) series -- 10 Mghz
>jcs> W (White) series -- I/O
>jcs>All used a negative logic (-3v = 1 and gnd = 0) and all used
>jcs>discretes in a technology known as DCD (diode-capacitor-diode).
They used negative voltage levels. DEC engineers, of course, used
mixed positive and negative logic. A -3v signal was a "0" or a "1"
as needed to make the logic as fast and simple as possible. I remember
interfacing with other vendors who had never heard of DeMorgan's laws
and kept trying to convince us that our logic couldn't work.
In more modern terms, folks who couldn't grok using a 7402 as an AND gate.
And of course we DREW them correctly, unlike a lot of people even
today who always draw 7400s as ANDs even when they are actually ORs.
And "DCD" referred to a gate used to make a triggering pulse from the
edge of a "level". I.e., clock a flipflop or generate a timing pulse
even though the input signal might stay asserted for a long time.
Not all of the circuits used that gate. The general logic family
was DTL.
>jcs>In 68 or 69 DEC introduced their M (Magenta) series which featured
>jcs>SSI devices on a standard module card.
There were also X-series modules. They had a yellow handle.
When I first saw these coming out of production I hit the
dictionary to confirm my recollection that "xanthic" means "yellow".
But when I complimented the guy in charge of such things, he looked
blankly at me. He didn't know from "xanthic". Yellow was just
a color that we hadn't used, and "X" was for "Xerox". They were
used in some 1970-ish large Xerox copiers.
>pg> The B212 flip-flop used on the PDP-10. Each flip-flop had a little pair
>pg> of delay lines on the inputs, just like the ones in the textbooks.
Yup. The problem was that no other design would give us a
guarantee of reliable operation on a register-pair swap. All the
other designs would guarantee a maximum time from clock pulse to
output change, but no MINIMUM time. And you can't swap two
registers if they have a ZERO clock-to-output time and ZERO setup
time. Since we had lived through a lot of flakiness in the PDP-6
(with the famous 6205 card) we bit the bullet and put in explicit
delays in the B212. There were a lot of those delay lines in the
machine. Added noticably to the manufacturing cost. The vendor
loved us.
Bob Clements, K1BC, clem...@bbn.com
In a former life, DEC badge #1047 and project engineer for the KA10.
Phil Gustafson
> [much edited for brevity, apologies if meanings mangled.]
>DEC engineers, of course, used
>mixed positive and negative logic. A -3v signal was a "0" or a "1"
>as needed to make the logic as fast and simple as possible.
>today who always draw 7400s as ANDs even when they are actually ORs.
>
foo(1)<high>
foo(1)<low>
foo(0)<high>
and
foo(0)<low>
This made it easy to understand what input did what to whom. The
wire-list program handled the mapping down to two physical terminals.