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Welcome to the Mechanical Sympathy group. This group is for discussing how to code sympathetically for the underlying stack/platform so good performance can be extracted.

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r r, Faraz Babar2

Nov 4

How to minimize the time difference between two threads performing timestamp writes?

Maybe some context is missing? There are way too many variables at play, the content of work 1 and 2

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How to minimize the time difference between two threads performing timestamp writes?

Maybe some context is missing? There are way too many variables at play, the content of work 1 and 2

Nov 4

Leonidas Kanarelis

May 7

Subject: Feedback wanted: Java 21 static graph runtime for low-latency in-process pipelines

Hi all, I would appreciate technical feedback on a Java 21 runtime I have been building: https://

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Subject: Feedback wanted: Java 21 static graph runtime for low-latency in-process pipelines

Hi all, I would appreciate technical feedback on a Java 21 runtime I have been building: https://

May 7

Вадик Рабочий, … Peter Veentjer9

Apr 22

Advice wanted on reducing p99 tail latency and scaling channel fan-out in Java RPC over Aeron

Thank you for the advice. Regarding the echo service, I initially made one like that, and at the

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Advice wanted on reducing p99 tail latency and scaling channel fan-out in Java RPC over Aeron

Thank you for the advice. Regarding the echo service, I initially made one like that, and at the

Apr 22

r r, … Peter12

Feb 18

Isolated CPU and cold start

I agree that one possible likely explanation is the one previously offered by deep.b - deep cstates.

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Isolated CPU and cold start

I agree that one possible likely explanation is the one previously offered by deep.b - deep cstates.

Feb 18

Peter Veentjer, … Daniel Marques8

2/17/25

Another memory order opaque question

And due to OOoE of modern microarchitectures, with acquire/release, the load can even be executed

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Another memory order opaque question

And due to OOoE of modern microarchitectures, with acquire/release, the load can even be executed

2/17/25

Peter Veentjer, Aleksey Shipilev2

1/22/25

Java opaque memory order

On 1/20/25 08:24, Peter Veentjer wrote: > The question is the following: assuming that an opaque

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Java opaque memory order

On 1/20/25 08:24, Peter Veentjer wrote: > The question is the following: assuming that an opaque

1/22/25

Vitor Tadashi, … john doe3

12/29/24

LMAX Disruptor vs Agrona RingBuffer (one consumer and one producer)

Are there any good examples of using Agrona/Aeron RingBuffers (1 to 1 or 1 to n) - threads only know

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LMAX Disruptor vs Agrona RingBuffer (one consumer and one producer)

Are there any good examples of using Agrona/Aeron RingBuffers (1 to 1 or 1 to n) - threads only know

12/29/24

Mark E. Dawson, Jr.

2/11/24

Deliberate vs. Intuitive CPU Affinity Brings PGO-like Performance Benefits

As a benchmark tool, I use a slightly modified version of Martin Thompson's InterThreadLatency

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Deliberate vs. Intuitive CPU Affinity Brings PGO-like Performance Benefits

As a benchmark tool, I use a slightly modified version of Martin Thompson's InterThreadLatency

2/11/24

Aleksandr Ivanov, … alarm...@gmail.com3

10/9/23

Correct use of memory barriers in atomic load/store impl for x86

"On x86 loads can only be reordered with store operations to a different memory location, since

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Correct use of memory barriers in atomic load/store impl for x86

"On x86 loads can only be reordered with store operations to a different memory location, since

10/9/23

Fred Castaneras, … Michael Barker4

6/11/23

Unsafe getLong/getLongVolatile has to read 8 bytes. It atomic / synchronized?

Hi Fred, As mentioned earlier, technically Unsafe.getLong could result in word tearing if another

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Unsafe getLong/getLongVolatile has to read 8 bytes. It atomic / synchronized?

Hi Fred, As mentioned earlier, technically Unsafe.getLong could result in word tearing if another

6/11/23

Mark E. Dawson, Jr.

2/22/23

Why I'm always suspicious of the 1st CPU Core on any socket

I have all my clients avoid pinning latency-sensitive threads to the first core of any CPU socket if

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Why I'm always suspicious of the 1st CPU Core on any socket

I have all my clients avoid pinning latency-sensitive threads to the first core of any CPU socket if

2/22/23

Alen Vrečko, … Martijn Verburg4

2/5/23

deoptimization insanity

I apologize for not following up on this sooner. Andrei, spot on with the deoptimizations on JDWP

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deoptimization insanity

I apologize for not following up on this sooner. Andrei, spot on with the deoptimizations on JDWP

2/5/23

12/23/22

Re: Abridged summary of mechanical-sympathy@googlegroups.com - 1 update in 1 topic

Which JVM and GC? Have you tried with other JVMs? On Tue, Dec 20, 2022 at 9:02 AM <mechanical-

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Re: Abridged summary of mechanical-sympathy@googlegroups.com - 1 update in 1 topic

Which JVM and GC? Have you tried with other JVMs? On Tue, Dec 20, 2022 at 9:02 AM <mechanical-

12/23/22

r r, Peter Veentjer3

10/24/22

JMM - is this program data race free?

Thanks a lot pon., 24 paź 2022, 05:09 użytkownik Peter Veentjer <alarm...@gmail.com> napisał

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JMM - is this program data race free?

Thanks a lot pon., 24 paź 2022, 05:09 użytkownik Peter Veentjer <alarm...@gmail.com> napisał

10/24/22

Antonio Rafael Rodrigues, Peter Veentjer5

9/18/22

Difference between set and lazySet on AtomicLong

Thank you very much Peter Veentjer, your answer was very clarifying. I think I should have mentioned

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Difference between set and lazySet on AtomicLong

Thank you very much Peter Veentjer, your answer was very clarifying. I think I should have mentioned

9/18/22

r r, Peter Veentjer6

9/15/22

volatile reads does happen before volatile write in JMM?

Thanks! czw., 15 wrz 2022 o 12:40 Peter Veentjer <alarm...@gmail.com> napisał(a): On Thu,

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volatile reads does happen before volatile write in JMM?

Thanks! czw., 15 wrz 2022 o 12:40 Peter Veentjer <alarm...@gmail.com> napisał(a): On Thu,

9/15/22

r r, … Avi Zohary10

9/12/22

Java Memory Model, ConcurrencyHashMap and guarantee of iterator

I'm not absolutely sure about this, but it is possible that each thread will be running on

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Java Memory Model, ConcurrencyHashMap and guarantee of iterator

I'm not absolutely sure about this, but it is possible that each thread will be running on

9/12/22

Mark E. Dawson, Jr.

8/26/22

Hunting down OS Noise and System Interrupts

The process of tracking system interrupts (from down in the HW to up in the OS/kernel) and locating

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Hunting down OS Noise and System Interrupts

The process of tracking system interrupts (from down in the HW to up in the OS/kernel) and locating

8/26/22

dor laor, Welly Tambunan2

7/14/22

Seastar's userspace tcp stack vs the kernel?

That's awesome way better than what AWS docs provide! Seems Aeron also provide DPDK transport

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Seastar's userspace tcp stack vs the kernel?

That's awesome way better than what AWS docs provide! Seems Aeron also provide DPDK transport

7/14/22

Peter Veentjer, … Mark Dawson14

7/3/22

Interrupts and hyperthreading.

I read Avi's response as simply concurring with mine - ie, that under *normal* low-latency

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Interrupts and hyperthreading.

I read Avi's response as simply concurring with mine - ie, that under *normal* low-latency

7/3/22

Roger Bergerin, … Mark Dawson4

6/26/22

Java x C++ Performance Battle => Interesting Article

I agree! Having worked with both C++ and Java top HFT firms, I know that both languages are capable

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Java x C++ Performance Battle => Interesting Article

I agree! Having worked with both C++ and Java top HFT firms, I know that both languages are capable

6/26/22

Mark E. Dawson, Jr., Gil Tene5

6/19/22

The "5-level Page Table" Default in Linux May Impact Throughput

Yes, I'm aware that ARM has offered LAM since long ago. And regarding LAM on Intel, we shouldn

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The "5-level Page Table" Default in Linux May Impact Throughput

Yes, I'm aware that ARM has offered LAM since long ago. And regarding LAM on Intel, we shouldn

6/19/22

Dain Ironfoot, … Laurynas Biveinis11

6/6/22

Compute in a lock free way

> > 128-bit > > atomics are more limited than 64-bit ones on x86_64, ie to load the >

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Compute in a lock free way

> > 128-bit > > atomics are more limited than 64-bit ones on x86_64, ie to load the >

6/6/22

5/1/22

Resource to learn JIT compiler

Thanks, watched it :). It is a great video that makes an overview of JVM / JIT optimizations. Do you

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Resource to learn JIT compiler

Thanks, watched it :). It is a great video that makes an overview of JVM / JIT optimizations. Do you

5/1/22

r r, Greg Young2

2/8/22

Resizable array, the fastest known approach

A bit older reference but worth benchmarking https://stackoverflow.com/questions/11621606/faster-way-

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Resizable array, the fastest known approach

A bit older reference but worth benchmarking https://stackoverflow.com/questions/11621606/faster-way-

2/8/22

r r, … Gil Tene6

2/8/22

Megamorphic virtual call optimization in Java

Thanks for your responses :) sobota, 5 lutego 2022 o 18:38:11 UTC+1 Gil Tene napisał(a): You might

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Megamorphic virtual call optimization in Java

Thanks for your responses :) sobota, 5 lutego 2022 o 18:38:11 UTC+1 Gil Tene napisał(a): You might

2/8/22

r r, Peter Veentjer3

7/29/21

Thread safety of the shared piece of memory - Java Memory Model

Thanks czwartek, 29 lipca 2021 o 20:30:46 UTC+2 alarm...@gmail.com napisał(a): There is a happens

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Thread safety of the shared piece of memory - Java Memory Model

Thanks czwartek, 29 lipca 2021 o 20:30:46 UTC+2 alarm...@gmail.com napisał(a): There is a happens

7/29/21

Gregory Golberg

7/25/21

Re: Digest for mechanical-sympathy@googlegroups.com - 1 update in 1 topic

Xs ed On Sat, Feb 6, 2016, 6:06 AM <mechanica...@googlegroups.com> wrote: mechanical-

dr.aygun...@gmail.com

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Re: Digest for mechanical-sympathy@googlegroups.com - 1 update in 1 topic

Xs ed On Sat, Feb 6, 2016, 6:06 AM <mechanica...@googlegroups.com> wrote: mechanical-

7/25/21

Gregory Golberg

7/25/21

Re: Digest for mechanical-sy x mpathy@google groups.com - 1 update in 1 topic

On Sat, Feb 6, 2016, 6:06 AM <mechanica...@googlegroups.com> wrote: mechanical-sympathy@

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Re: Digest for mechanical-sy x mpathy@google groups.com - 1 update in 1 topic

On Sat, Feb 6, 2016, 6:06 AM <mechanica...@googlegroups.com> wrote: mechanical-sympathy@

7/25/21

Mark E. Dawson, Jr.

7/16/21

Intel may be giving TLB Shootdowns a makeover soon

Intel is considering moving some of the kernel-based responsibilities of handling TLBs into hardware

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Intel may be giving TLB Shootdowns a makeover soon

Intel is considering moving some of the kernel-based responsibilities of handling TLBs into hardware

7/16/21

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