Dual-ported SRAM (1RW,1R) on Sky130

[Anuj Dubey]

Hi,

I am trying to compile a dual-port SRAM with one read/write and one read port targeting the Skywater 130nm technology. I have the following questions.

1. Is there a limit to the SRAM size, in terms of the number of bits?

2. I did not find the complete library for Sky130 in the github clone of OpenRAM: https://github.com/VLSIDA/OpenRAM

Is it available somewhere, or is there a way to build/generate the missing library cell folders like gds_lib, sp_lib, tf, etc., in the technology/sky130 folder?

I did find a repo where this is probably done but I am not sure if it has the most updated libraries: https://github.com/vsdip/vsdsram_sky130/tree/main/OpenRAM/sky130A

I succeeded in building a single ported (1 RW) SRAM with32768 bits (32x1024) using the files from the above mentioned repo. Next I modified the config file fields accordingly to compile a dual-ported SRAM (RW=1, R=1) of size 32768 bits:

word_size=32
num_words=1024
num_rw_ports = 1

num_r_ports = 1
write_size = 4
tech_name="sky130A"
process_corners=["TT"]
supply_voltages=[1.8]
output_path="sky130_ram_32x1024_1rw_1r"
output_name="sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

But I get the following error:

** Start: 02/27/2022 21:18:17
Technology: sky130A
Total size: 32768 bits
Word size: 32
Words: 1024
Banks: 1
Write size: 4
RW ports: 1
R-only ports: 1
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
ERROR: file design.py: line 46: Custom cell pin names do not match spice file:
['bl0', 'br0', 'bl1', 'br1', 'wl0', 'wl1', 'vdd', 'gnd'] vs []
Traceback (most recent call last):
  File "/home/anuj/OpenRAM/compiler/openram.py", line 54, in <module>
    c = sram_config(word_size=OPTS.word_size,
  File "/home/anuj/OpenRAM/compiler/sram/sram_config.py", line 44, in __init__
    self.compute_sizes()
  File "/home/anuj/OpenRAM/compiler/sram/sram_config.py", line 73, in compute_sizes
    bitcell = factory.create(module_type=OPTS.bitcell)
  File "/home/anuj/OpenRAM/compiler/sram_factory.py", line 142, in create
    obj = mod(name=module_name, **kwargs)
  File "/home/anuj/OpenRAM/compiler/bitcells/bitcell_2port.py", line 22, in __init__
    super().__init__(name, prop=props.bitcell_2port)
  File "/home/anuj/OpenRAM/compiler/bitcells/bitcell_base.py", line 21, in __init__
    design.design.__init__(self, name, cell_name, prop)
  File "/home/anuj/OpenRAM/compiler/base/design.py", line 46, in __init__
    debug.check(prop.port_names == self.pins,
  File "/home/anuj/OpenRAM/compiler/debug.py", line 33, in check
    assert 0

AssertionError

So I was wondering if someone could help me compile a dual-ported SRAM with the (preferably recent) Sky130 library cells.

Thanks,

Anuj

ᐧ

[Matthew Guthaus]

Hi,

I responded to your question in the Skywater slack...

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Professor, Computer Science & Engineering

Baskin School of Engineering

University of California Santa Cruz

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[Rags Hp]

Hello Sir,

I encountered with same problem as Anuj did in above conversation. i am not able to generate memory with dual port configurations as mentioned. Also i couldn't follow the solution at the place where you mentioned as "Skywater slack...".

where do i find solution for same. I have sky130A tech files in tech folder. request you to provide solution so that i can move ahead.

Pasting the error:

python3 openram.py myconfig_sky130.py
|==============================================================================|
|=========                      OpenRAM v1.1.17                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-u...@ucsc.edu           =========|
|=========        Development help: openram-...@ucsc.edu        =========|
|=========         Temp dir: /tmp/openram_pdlab_476533_temp/          =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 07/09/2022 17:43:21
Technology: sky130A
Total size: 8192 bits
Word size: 8
Words: 1024
Banks: 1

RW ports: 1
R-only ports: 1
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).

Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).

Only generating nominal corner timing.

ERROR: file design.py: line 46: Custom cell pin names do not match spice file:
['bl0', 'br0', 'bl1', 'br1', 'wl0', 'wl1', 'vdd', 'gnd'] vs []
Traceback (most recent call last):

  File "/home/pdlab/Memories/SRAM_generators/OpenRAM-stable/compiler/openram.py", line 54, in <module>
    c = sram_config(word_size=OPTS.word_size,
  File "/home/pdlab/Memories/SRAM_generators/OpenRAM-stable/compiler/sram/sram_config.py", line 44, in __init__
    self.compute_sizes()
  File "/home/pdlab/Memories/SRAM_generators/OpenRAM-stable/compiler/sram/sram_config.py", line 58, in compute_sizes
    bitcell = factory.create(module_type=OPTS.bitcell)
  File "/home/pdlab/Memories/SRAM_generators/OpenRAM-stable/compiler/sram_factory.py", line 142, in create
    obj = mod(name=module_name, **kwargs)
  File "/home/pdlab/Memories/SRAM_generators/OpenRAM-stable/compiler/bitcells/bitcell_2port.py", line 22, in __init__
    super().__init__(name, prop=props.bitcell_2port)
  File "/home/pdlab/Memories/SRAM_generators/OpenRAM-stable/compiler/bitcells/bitcell_base.py", line 21, in __init__
    design.design.__init__(self, name, cell_name, prop)
  File "/home/pdlab/Memories/SRAM_generators/OpenRAM-stable/compiler/base/design.py", line 46, in __init__
    debug.check(prop.port_names == self.pins,
  File "/home/pdlab/Memories/SRAM_generators/OpenRAM-stable/compiler/debug.py", line 33, in check
    assert 0
AssertionError

Thanks in advance