OpenRAM Tool technical question

[Jeanfranco Araujo]

Hello,

My name is Jeanfranco Araujo, I am part of a team that is currently
using the OpenRAM V1.1.7 to create a memory.

During the process of compiling all our cells, we came across an issue
with the routing of the created memory. More precisely, in the DFF routing.

After further analysis on the OpenRam code we found that the issue came
from the file dff_inv_array.py Line 167. Seems like the OpenRam compiler
expects the pins for the clock to be specifically on metal_2(m2) layer
and the router will do the connection regardless of any other m2 contact
in the way, subsequently shorting anything in its way.


The question is, are there standard rules (Documentation) for specific
cells that need to be obey to avoid this type of issue? For example,
trying to avoid the use of the m2 layer on the D-Flipflop cell.


Also, while checking information online, we came across this:
https://github.com/VLSIDA/OpenRAM/issues/69

Which based on that information, I am assuming that only 4 cells (dff,
bitcell, sense_amp, and write_driver) need to be specifically design to
obey some type of standard in the code to avoid the issue explained
above. Is this correct?


Thank you for your time,

Sincerely,

--
Jeanfranco Araujo
Hardware Engineer
IDEAS Engineering and Technology, LLC
10520 Research Rd. SE Suite 100
Albuquerque, NM 87123