Problem generating 1rw bitmasked RAM

[Dan Petrisko]

Hello! I am able to successfully generate full word memories, but am having trouble generating bitmasked memories.

```

# Data word size

word_size = 15

# Number of words in the memory

num_words = 64

# Port configuration (1-2 ports allowed)

num_r_ports = 0

num_w_ports = 0

num_rw_ports = 1

# Write mask size

write_size = 1

# Technology to use in $OPENRAM_TECH

tech_name = "freepdk45"

nominal_corner_only = True

# Output directory for the results

output_path = "results"

# Output file base name

output_name = "free45_1rw_d64_w15_bit"

# Disable analytical models (requires SPICE)

#analytical_delay = False

```

```

Traceback (most recent call last):

  File "path/openram/compiler/openram.py", line 78, in <module>

    name=OPTS.output_name)

  File "path/openram/compiler/sram/sram.py", line 44, in __init__

    self.s.create_netlist()

  File "path/openram/compiler/sram/sram_base.py", line 173, in create_netlist

    self.add_modules()

  File "path/openram/compiler/sram/sram_base.py", line 375, in add_modules

    self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank")

  File "path/openram/compiler/sram_factory.py", line 136, in create

    obj = mod(name=module_name, **kwargs)

  File "path/openram/compiler/modules/bank.py", line 51, in __init__

    self.create_netlist()

  File "path/openram/compiler/modules/bank.py", line 61, in create_netlist

    self.add_modules()

  File "path/openram/compiler/modules/bank.py", line 405, in add_modules

    bit_offsets=self.bit_offsets)

  File "path/openram/compiler/sram_factory.py", line 136, in create

    obj = mod(name=module_name, **kwargs)

  File "path/openram/compiler/modules/port_data.py", line 49, in __init__

    self.create_netlist()

  File "path/openram/compiler/modules/port_data.py", line 73, in create_netlist

    self.add_modules()

  File "path/openram/compiler/modules/port_data.py", line 247, in add_modules

    write_size=self.write_size)

  File "path/openram/compiler/sram_factory.py", line 136, in create

    obj = mod(name=module_name, **kwargs)

  File "path/openram/compiler/modules/write_mask_and_array.py", line 39, in __init__

    self.create_layout()

  File "path/openram/compiler/modules/write_mask_and_array.py", line 47, in create_layout

    self.place_and2_array()

  File "path/openram/compiler/modules/write_mask_and_array.py", line 95, in place_and2_array

    self.wmask_en_len))

  File "path/openram/compiler/debug.py", line 32, in check

    assert 0

AssertionError

```

WMASK: 1.41 AND2: 1.4375

Best,

Dan

[Matthew Guthaus]

Hi Dan,

There should be an error message right before the trace back:

ERROR: file write_mask_and_array.py: line 94: Write mask AND is wider than the corresponding write drivers 1.4375 vs 1.41.

This means that the and gate is too wide so it can't do a single bit write mask, unfortunately. You would need to make a custom AND gate or increase the write mask size.

Matt

[Daniel Petrisko]

Thanks!

Is there a guide somewhere of acceptable ranges of parameter combinations? Just width, depth and mask would be useful

- Dan

[Matthew Guthaus]

This depends on each technology, so there isn't a list. In this case, it doesn't fit, but it may work in another technology.

Matt