Invalid number of RBLs for port configuration

[clément]

Hello,

First, thanks for this amazing project. 

I tried generating RAMs with more than 2 ports (e.g. 1 wr and 2 rd) with freePDK45 and it fails.

Is this supposed to be supported ? I imagined it was after reading the paper "Automated Synthesis of Multi-Port Memories and Control".

The script is well identifying that there is no specific bitcell associated to that configuration and selects the parameterized bitcell. Though, there is an issue with replica bit lines (replica_bitcell_array.py line 56). I imagine it's expecting to get 3 because of the number of ports but only gets 2. The code seems to be designed to manage only 2 RBLs: 1 on the left if only 1 port and 1 on the right if more than 1 port. 

I join the config file used to test it.

Best regards,

Clément

[Matthew Guthaus]

Hi Clement,

We have the infrastructure (timing, netlist, etc.) for >2 ports, but not the layout. RIght now, we use only 4 metal layers and a third port would not fit on the bottom/left or top/right, so we would need to use more layers and implement that.

Sorry!

Matt

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Matthew Guthaus

Associate Dean of Graduate Studies

Professor, Computer Science & Engineering

Baskin School of Engineering

University of California Santa Cruz

https://www.soe.ucsc.edu/people/mrg