Error during characterization

[Vincenzo Giannone]

Good morning,

my name is Vincenzo Giannone and I'm trying to create a memory with 2 read ports and 1 write port. I met the following problem related to the creation of output liberty file:

ERROR: file simulation.py: line 676: Could not find ['rbl0', 'rbl1'] net in timing paths.
Traceback (most recent call last):
  File "~/OpenRAM/compiler/openram.py", line 80, in <module>
    s.save()
  File "~/OpenRAM/compiler/sram/sram.py", line 107, in save
    functional(self.s,
  File "~/OpenRAM/compiler/characterizer/functional.py", line 82, in __init__
    self.set_internal_spice_names()
  File "~/OpenRAM/compiler/characterizer/simulation.py", line 592, in set_internal_spice_names
    rbl0_name_port, rbl1_name_port = self.get_bl_name_multiport(self.graph.all_paths)
  File "~/OpenRAM/compiler/characterizer/simulation.py", line 712, in get_bl_name_multiport
    rbl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
  File "~/OpenRAM/compiler/characterizer/simulation.py", line 676, in get_alias_in_path
    debug.error("Could not find {} net in timing paths.".format(internal_net), 1)
  File "~/OpenRAM/compiler/debug.py", line 47, in error
    assert return_value == 0
AssertionError

rbl0 and rbl1 are the names of the read bitlines.

Could you help me to solve that issue, please?

Best regards,

Vincenzo Giannone

[Matthew Guthaus]

Hi,

First, we do not support >2 ports at this time in layout and haven't really tested it with that for netslists.

Please make sure you are using an updated version. What version (commit id) are you using?

Also, please share a config file so we can replicate what you are doing.

Thanks,

matt

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[Matthew Guthaus]

I see. The characterizer keeps track of the "paths" for characterization and it seems like the modifications have messed that up.  Since we haven't tested two read ports, there might be a bug in that as well. 

Matt

On Mon, Feb 28, 2022 at 11:16 AM Vincenzo Giannone <giannonev...@gmail.com> wrote:

I have modified source code and I have integrated all the spice and gds files needed to generate a memory with 2 read ports and 1 write port. 

When I will complete my work, I will publish all on Github. I'm currently working on version 1.1.18.

The only missing aspect regards the characterization of the memory by using elmore model. When I launch the compilation I get that error

concerning the fact that the list self.graph.all_paths is empty. 

Configuration File is the following one:

word_size = 32
num_words = 64

num_rw_ports = 0
num_r_ports = 2
num_w_ports = 1
num_all_ports = num_rw_ports + num_r_ports + num_w_ports

tech_name = "sky130A"
nominal_corner_only = False
process_corners = ["TT"]
supply_voltages = [1.8]
temperatures = [25]

RF_mode = True
route_supplies = True
check_lvsdrc = True

output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
                                                      num_r_ports,
                                                      num_w_ports,
                                                      word_size,
                                                      num_words,
                                                      tech_name)
output_path = "macro/{}".format(output_name)

RF_mode is a variable that I introduced to differentiate the generation of a 1rw port memory that is natively supported from my 2r1w Register File.

Thank you,

Vincenzo Giannone