inline lvsdrc error

[Joy T]

Hi Experts, 

I am trying to run some basic examples in readme and I found LVS errors in bitcell_array using scn4m_subm tech node. 

The log output is 

python3 compiler/openram.py cfg3.py

|==============================================================================|

|=========                      OpenRAM v1.1.19                       =========|

|=========                                                            =========|

|=========               VLSI Design and Automation Lab               =========|

|=========        Computer Science and Engineering Department         =========|

|=========            University of California Santa Cruz             =========|

|=========                                                            =========|

|=========          Usage help: openram-u...@ucsc.edu           =========|

|=========        Development help: openram-...@ucsc.edu        =========|

|=========         Temp dir: /tmp/openram_zhaten01_5874_temp/         =========|

|=========                See LICENSE for license info                =========|

|==============================================================================|

** Start: 12/23/2021 03:31:45

Technology: scn4m_subm

Total size: 32 bits

Word size: 2

Words: 16

Banks: 1

Write size: None

RW ports: 1

R-only ports: 0

W-only ports: 0

Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).

Only generating nominal corner timing.

Words per row: 1

Output files are:

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.lvs

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.sp

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.v

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.lib

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.py

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.html

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.log

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.lef

/home/zhaten01/work/OpenRAM/cfg3_lvsdrc/sram_16_2_scn4m_subm.gds

ERROR: file magic.py: line 349: bitcell_array   LVS mismatch (results in /tmp/openram_zhaten01_5874_temp/bitcell_array.lvs.report)

ERROR: file hierarchy_design.py: line 71: LVS failed for bitcell_array with 3 errors(s)

Traceback (most recent call last):

  File "compiler/openram.py", line 78, in <module>

    name=OPTS.output_name)

  File "/home/zhaten01/work/OpenRAM/compiler/sram/sram.py", line 48, in __init__

    self.s.create_netlist()

  File "/home/zhaten01/work/OpenRAM/compiler/sram/sram_base.py", line 197, in create_netlist

    self.add_modules()

  File "/home/zhaten01/work/OpenRAM/compiler/sram/sram_base.py", line 482, in add_modules

    self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank")

  File "/home/zhaten01/work/OpenRAM/compiler/sram_factory.py", line 142, in create

    obj = mod(name=module_name, **kwargs)

  File "/home/zhaten01/work/OpenRAM/compiler/modules/bank.py", line 52, in __init__

    self.create_netlist()

  File "/home/zhaten01/work/OpenRAM/compiler/modules/bank.py", line 62, in create_netlist

    self.add_modules()

  File "/home/zhaten01/work/OpenRAM/compiler/modules/bank.py", line 391, in add_modules

    rows=self.num_rows)

  File "/home/zhaten01/work/OpenRAM/compiler/sram_factory.py", line 142, in create

    obj = mod(name=module_name, **kwargs)

  File "/home/zhaten01/work/OpenRAM/compiler/modules/replica_bitcell_array.py", line 71, in __init__

    self.create_netlist()

  File "/home/zhaten01/work/OpenRAM/compiler/modules/replica_bitcell_array.py", line 81, in create_netlist

    self.add_modules()

  File "/home/zhaten01/work/OpenRAM/compiler/modules/replica_bitcell_array.py", line 112, in add_modules

    rows=self.row_size)

  File "/home/zhaten01/work/OpenRAM/compiler/sram_factory.py", line 142, in create

    obj = mod(name=module_name, **kwargs)

  File "/home/zhaten01/work/OpenRAM/compiler/modules/bitcell_array.py", line 31, in __init__

    self.create_layout()

  File "/home/zhaten01/work/OpenRAM/compiler/modules/bitcell_array.py", line 51, in create_layout

    self.DRC_LVS()

  File "/home/zhaten01/work/OpenRAM/compiler/base/hierarchy_design.py", line 71, in DRC_LVS

    self.lvs_errors))

  File "/home/zhaten01/work/OpenRAM/compiler/debug.py", line 33, in check

    assert 0

AssertionError

and my config file is: 

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

# Data word size

word_size = 2

# Number of words in the memory

num_words = 16

# Technology to use in $OPENRAM_TECH

tech_name = "scn4m_subm"

# You can use the technology nominal corner only

nominal_corner_only = True

# Or you can specify particular corners

# Process corners to characterize

# process_corners = ["SS", "TT", "FF"]

# Voltage corners to characterize

# supply_voltages = [ 3.0, 3.3, 3.5 ]

# Temperature corners to characterize

# temperatures = [ 0, 25 100]

# Output directory for the results

output_path = "cfg3_lvsdrc"

# Output file base name

#output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

output_name = "sram_{0}_{1}_{2}".format(num_words,word_size,tech_name)

check_lvsdrc=True

inline_lvsdrc=True

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Is this error expected? 

Appreciate your help. 

--

-- Regards, Joy. 

[Matthew Guthaus]

Hi Joy,

Can you let us know what version of magic and netgen you are using? There are some recent changes that may have broken things...

Also, what commit of OpenRAM?

Thanks,

Matt

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https://openram.soe.ucsc.edu
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