Disabled port power
9 views
Skip to first unread message
David Ratchkov
Aug 22, 2019, 5:29:17 PM8/22/19
to openram-...@ucsc.edu
Hi,
i was experiementing with teh OpenRAM compiler. I noticed that the Liberty data for disabled power is hardcoded to 0. I added a measurement, where the port is disabled and held in read/write states (as applicable), data and address are held steady as well, only clock is toggled.
I see this from measurement.
read1_power1 = 8.495852e-05 from= 1.300000e-07 to= 1.400000e-07
read0_power1 = 8.522923e-05 from= 5.000000e-08 to= 6.000100e-08
disabled_read1_power1= 6.798398e-05 from= 1.100000e-07 to= 1.200010e-07
disabled_read0_power1= 6.313486e-05 from= 6.000000e-08 to= 7.000100e-08
As you can see, disabeld power is not that much lower than active power. Is this expected?
Here is the control signal setup. Let me know if you need the spice files for something.
* Generation of control signals
* (time, data): [(0, 1), (10.0, 0), (20.0, 0), (30.0, 1), (40.0, 1), (50.0, 1), (60.0, 1), (70.0, 1), (80.0, 0), (90.0, 1), (100.0, 0), (110.0, 1), (120.0, 1), (130.0, 1), (140.0, 1)]
VCSB0 CSB0 0 PWL (0n 1.0v 9.48n 1.0v 9.52n 0.0v 19.48n 0.0v 19.52n 0.0v 29.48n 0.0v 29.52n 1.0v 39.48n 1.0v 39.52n 1.0v 49.48n 1.0v 49.52n 1.0v 59.48n 1.0v 59.52n 1.0v 69.48n 1.0v 69.52n 1.0v 79.48n 1.0v 79.52n 0.0v 89.48n 0.0v 89.52n 1.0v 99.48n 1.0v 99.52n 0.0v 109.48n 0.0v 109.52n 1.0v 119.48n 1.0v 119.52n 1.0v 129.48n 1.0v 129.52n 1.0v 139.48n 1.0v 139.52n 1.0v )
* (time, data): [(0, 1), (10.0, 1), (20.0, 1), (30.0, 1), (40.0, 0), (50.0, 0), (60.0, 1), (70.0, 1), (80.0, 1), (90.0, 1), (100.0, 1), (110.0, 1), (120.0, 0), (130.0, 0), (140.0, 1)]
VCSB1 CSB1 0 PWL (0n 1.0v 9.48n 1.0v 9.52n 1.0v 19.48n 1.0v 19.52n 1.0v 29.48n 1.0v 29.52n 1.0v 39.48n 1.0v 39.52n 0.0v 49.48n 0.0v 49.52n 0.0v 59.48n 0.0v 59.52n 1.0v 69.48n 1.0v 69.52n 1.0v 79.48n 1.0v 79.52n 1.0v 89.48n 1.0v 89.52n 1.0v 99.48n 1.0v 99.52n 1.0v 109.48n 1.0v 109.52n 1.0v 119.48n 1.0v 119.52n 0.0v 129.48n 0.0v 129.52n 0.0v 139.48n 0.0v 139.52n 1.0v )
* Generation of Port clock signal
* PULSE: period=10.0
VCLK0 CLK0 0 PULSE (0 1.0 10.0n 0.04n 0.04n 4.960000000000001n 10.0n)
* PULSE: period=10.0
VCLK1 CLK1 0 PULSE (0 1.0 10.0n 0.04n 0.04n 4.960000000000001n 10.0n)
* Measure statements for delay and power
* Cycle 0 Port All 0.00 ns: : Idle cycle (no positive clock edge)
* Cycle 1 Port 0 10.00 ns: : W data 1 address 0000011
* Cycle 2 Port 0 20.00 ns: : W data 0 address 1111111 to write value
* Cycle 3 Port 0 30.00 ns: : Clock only on port 0
* Cycle 4 Port 1 40.00 ns: : R data 1 address 0000011 to set DOUT caps
* Cycle 5 Port 1 50.00 ns: : R data 0 address 1111111 to check W0 worked
* Cycle 6 Port 1 60.00 ns: : Clock only on port 1
* Cycle 7 Port All 70.00 ns: : Idle cycle (if read takes >1 cycle)
* Cycle 8 Port 0 80.00 ns: : W data 1 address 1111111 to write value
* Cycle 9 Port 0 90.00 ns: : Clock only on port 0
* Cycle 10 Port 0 100.00 ns: : W data 0 address 0000011 to clear DIN caps
* Cycle 11 Port 1 110.00 ns: : Clock only on port 1
* Cycle 12 Port 1 120.00 ns: : R data 0 address 0000011 to clear DOUT caps
* Cycle 13 Port 1 130.00 ns: : R data 1 address 1111111 to check W1 worked
* Cycle 14 Port All 140.00 ns: : Idle cycle (if read takes >1 cycle))
Matthew Guthaus
Aug 22, 2019, 6:05:40 PM8/22/19
to openram-...@ucsc.edu
Hi David,
How did you disable the port? Set csb to 1?
In you set csb to 1, this would leave just the power of the flops that capture the control bits, address and data input. The rest of the power is leakage which can also be fairly big in memories.
Matt
--
https://openram.soe.ucsc.edu
---
You received this message because you are subscribed to the Google Groups "OpenRAM Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to openram-dev-gr...@ucsc.edu.
To view this discussion on the web visit https://groups.google.com/a/ucsc.edu/d/msgid/openram-dev-group/1D3756AD-8DC8-4D71-AAFC-BF1F86F50F02%40thracesystems.com.
Matthew Guthaus
Associate Dean of Graduate Studies
Professor, Computer Science & Engineering
Baskin School of Engineering
University of California Santa Cruz
Reply all
Reply to author
Forward
0 new messages