Sorry for not finishing this by DDL, but post my story briefly
Jian Zhang
Hi, everyone,
The deadline is coming. I am afraid I cannot finish this by the DDL. But here I will tell you what I have been doing in the last one month.
[Basic self-introduction]
This is Jack Zhang from Shanghai. This July, I just received a master degree of mechanical engineering from school. Now I am working as a sw engineer in a big IC company.
I got started in learning CPU design 3~4 years ago. I designed a single cycled MIPS32 soc(12 basic instructions), with a tetris game run on it, including 3k lines of assembly for the tetris game. And thousand lines of verilog for cpu and verilog design.
Early this year, I learned mipsfpga+ project. Now I could run linux on my FPGA board. It's a pure verilog project.
This October, I heard of this contest. I decided to sign up for that, because I think it would be a great opportunity to put what I learned together. I believe RISCV will definitely be a great trend in the next few years. Actually, the first impression RISCV gave me is not good. I felt toolchain is too complicated, and community is complicated, I cannot set up a usable environment with ease. This is why I didn't do much in RISCV in the last few years. Actually I heard the name of riscv in the early 2015. I wish to get started in RISCV practically after this contest.
[Project status]
During the last month, I was working with Shaomin Zhai to fight for this contest. We together met nearly every night. There are many nights we stayed up late to 12~2 a.m. We solved a lot of problems and get more and more achievements.
But actually I was lack of time to finish this contest. e.g. I had a lot work to do in my daily job, I only had 3 hours every work day. Plus I had to attend a wedding one weekend and my aunt had a car accident, and I had to look after her one weekend. My real work hours in the contest was limited.
Back to the project, currently I am using one open core(based on scr1) and debugging a pure verilog ahb peripheral system(based on mipsfpga+) with my altera DE1-SOC board. The reason why I didn't reuse microsemi HPMS peripheral system is that it's not vendor independent enough! The attachment is my design arch diagram, Now, the whole soc system could load code (srec form). And print messages into the sw uart.
But I still have some steps to do:
- the cpu core is written in system verilog, I need to convert it to verilog
- dhrysone and zephyr need to be ported. But I have some reference codes in scr1, it could run dhrystone and zephyr 1.0.9 natively. So porting wouldn't be a big problem for me.
- put all the code to fit into microsemi yellow board. It is feasible because my whole project is pure verilog-style.
[Achievement lists]
The following is a list of what I did int the last month.
10.12-10.18,
learned microsemi dev tools( libero SOC, and softconsole)
set up riscv-tools
initial research in zephyr, dhrystone,compliance test
10.19-11.1
designed not to use microsemi softconsole toolchain, or HAL library, because some compatible problems
sketched a detailed diagram of araine(an open source project).
succeeded in debugged a uart verilog module
extracted a pure verilog ahb peripheral from mipsfpga+ project
11.1-11.10
study current open cores/soc solution.
study e200
study araine
study picorv32
others like(pulp-riscv/RV12 and etc)
But nearly each one have problems after I tested. Like language(sv, verliog), like peipherals(qsys, or vendor dependent ip catalog) arch (64bit/32bit, pipeline stages, Branch predict unit, cache, TCM ). After many failure and lessons, I decided to use scr1 by the end of 11.10
11.10-11.20
the time I decide the core is very late. It means only 2 weeks left.
learned verilator
reproduce scr1
noticed scr1 used qsys system(altera dependent peripheral system), need to port a different peripheral system that microsemi board can use.
Started to porting pure verilog peripheral system.
Porting a hardware uart loader
11.20-11.26
Designed memory architecture, finally decide to use harvard architechure.
With inst mem only readable, I need to manage the memory layout more reasonably with linker file.
Learned linker script.
more debug in uart loader and uart modules
c program could print helloworld to uart! (last night)
