adapting Zephyr to a new platform?

[Eric Smith]

If anyone has already done the work of adapting Zephyr to a new platform, what did you have to do?

I was hoping to take the HiFive1 support and tweak it for my core; I mostly just need to change the memory map and a little bit of the from-reset startup code. I intend to have RAM addressed from 0x00000000 up, with reset starting at 0x00000000. My core has a little bit of special stuff near 0, so at address 0 I need to have a jump instruction to the real code.

I've already gotten lost trying to figure out the linker script; I can't figure out where the variable definitions for CONFIG_RISCV_ROM_BASE_ADDR, CONFIG_RISCV_ROM_SIZE, CONFIG_RISCV_RAM_BASE_ADDR, and RISCV_RAM_SIZE are supposed to be.  It looks like there are non-RISCV-specific definitions for CONFIG_FLASH_BASE_ADDRESS and CONFIG_SRAM_BASE_ADDRESS, but I haven't really found where those are set either.

If need be, I can change my RAM base address, but I'd prefer not to.

Thanks in advance!

Eric

[Nelson Ribeiro]

My github repo is messy (WIP...), but I have a patch with my modifications:

https://github.com/ng2rdev/riscv-contest-2018/blob/master/scripts/riscv-zephyr-ngrriscv.patch

You can also compare the original version with 

https://github.com/SpinalHDL/zephyr/tree/21cdcee1145d4c36e3ce94df6a403696bc4c2068

Nelson

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[Eric Smith]

On Fri, Nov 16, 2018 at 4:33 PM Nelson Ribeiro <ngrr.r...@gmail.com> wrote:

My github repo is messy (WIP...), but I have a patch with my modifications:

Thank you!

[Nelson Ribeiro]

I cannot guarantee that my implementation works, but examples do compile and I checked the objdump output, and they seemed OK.

Nelson

[Nelson Ribeiro]

Ah, with those sizes for Rom and Ram defined, one of the examples do not compile. I beleive that you need slightly more than 16kbytes of Rom defined.

Nelson

[Antti Lukats]

On Saturday, 17 November 2018 00:51:39 UTC+1, Nelson Ribeiro wrote:

Ah, with those sizes for Rom and Ram defined, one of the examples do not compile. I beleive that you need slightly more than 16kbytes of Rom defined.

Nelson

I have also seen that 16K ROM is not sufficient, for Zephyr

https://github.com/micro-FPGA/riscv-contest-2018/wiki/SoC-Design

I guess about 20K + 4K is minimal, 32K shared code/data works in any case

g

Antti

[Frank Buss]

And here you can see how Antti did it, with the very useful "compare" function of Github:

https://github.com/zephyrproject-rtos/zephyr/compare/v1.13-branch...micro-FPGA:v1.13-branch

Similar to what Nelson did.

But you don't have to modify Zephyr. I enhanced my emulator, it is now qemu compatible, at least regarding the required functionality for the Zepyhr programs, which doesn't need that much extra functions:

https://gist.github.com/FrankBuss/c974e59826d33e21d7cad54491ab50e8

It runs the philosophers and synchronization applications, and passes all 55 compliance tests. Instructions how to compile and use it are at the beginning of the code.

It wasn't easy to find all information about the details of how interrupts, exceptions and ECALLs work. I tried to summarize it in this posting, if someone else is struggling with it:

https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/kXgfFqgBv-c/V_midA9GAgAJ

Now I guess I could just compile the C code for a 6502 core, but it wouldn't beat the 220 LUTs of the smallest design. Looks like still some work to do, but I have some ideas.