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RISC-V Soft CPU Discussion

1–30 of 63

This is a public discussion group open for anyone to join and setup as a discussion group for participants in the fall 2018 RISC-V soft CPU contest.

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Jian Zhang, Jack Kang2

Jan 30

Sorry for not finishing this by DDL, but post my story briefly

My dear friend. I am from China.I think your name is also like a chinese man. I want to read

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Sorry for not finishing this by DDL, but post my story briefly

My dear friend. I am from China.I think your name is also like a chinese man. I want to read

Jan 30

Kevin Eyssartier

10/7/19

Thales RISC-V security contest

Hello everyone and thank you for your interest in this contest. We are happy to see this much

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Thales RISC-V security contest

Hello everyone and thank you for your interest in this contest. We are happy to see this much

10/7/19

RISC-V Community Response Team

9/25/19

RISC-V Community Group Changes

Hello RISC-V Community, As a followup to the recent publication of the Code of Conduct and the lively

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RISC-V Community Group Changes

Hello RISC-V Community, As a followup to the recent publication of the Code of Conduct and the lively

9/25/19

Frank Buss, … Jörg Mische12

9/24/19

RISC-V security contest

Sorry, here the correct URL to the Libero installation howto: https://bobbl.github.io/fpga/microsemi/

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RISC-V security contest

Sorry, here the correct URL to the Libero installation howto: https://bobbl.github.io/fpga/microsemi/

9/24/19

Frank Buss, … Changyi Gu9

8/24/19

Physical Memory Protection (PMP)

Hi, Frank Sorry for the late reply. I just saw your post. And I'm also planning to joining the

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Physical Memory Protection (PMP)

Hi, Frank Sorry for the late reply. I just saw your post. And I'm also planning to joining the

8/24/19

Jeffrey Osier-Mixon

7/11/19

RISC-V Community Code of Conduct

This is a message authorized by Dave Patterson, RISC-V Board of Directors Vice Chair Following the

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RISC-V Community Code of Conduct

This is a message authorized by Dave Patterson, RISC-V Board of Directors Vice Chair Following the

7/11/19

1/4/19

Mi-V softcore with Libero v2.3 for PolarFire data initialization

I am attempting to run FreeRTOS on a Mi-V softcore on a Microsemi PolarFire FPGA using Libero v2.3

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Mi-V softcore with Libero v2.3 for PolarFire data initialization

I am attempting to run FreeRTOS on a Mi-V softcore on a Microsemi PolarFire FPGA using Libero v2.3

1/4/19

Antti Lukats, … Nelson Ribeiro13

12/6/18

Prize announcement and aftermath

Actually, your implementation is perfect for ice40, because you can have 16(signed/unsigned) x 16 (

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Prize announcement and aftermath

Actually, your implementation is perfect for ice40, because you can have 16(signed/unsigned) x 16 (

12/6/18

Richard Miller, … Nicolas Bértolo6

12/5/18

Assertion failure in philosophers sample program

We found the same problem in our implementation. It turned out to be a Zephyr bug. This patch has

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Assertion failure in philosophers sample program

We found the same problem in our implementation. It turned out to be a Zephyr bug. This patch has

12/5/18

11/29/18

Bay area Yosys meeting, tomorrow 6pm

Hi Just reposting Cliffords tweet, for those who did not see it and are in the area https://twitter.

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Bay area Yosys meeting, tomorrow 6pm

Hi Just reposting Cliffords tweet, for those who did not see it and are in the area https://twitter.

11/29/18

11/27/18

First actual use of the SoftCPU designed for the contest !

Hi this morning fresh from vapor oven, this boards arrived: About 2 hours later the verilog code is

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First actual use of the SoftCPU designed for the contest !

Hi this morning fresh from vapor oven, this boards arrived: About 2 hours later the verilog code is

11/27/18

Eric Smith, … Federico Tula Rovaletti16

11/27/18

It's dead, Jim!

Here is our story... The project was done by my students: - Santiago Abbate (graduate) - Nicolas

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It's dead, Jim!

Here is our story... The project was done by my students: - Santiago Abbate (graduate) - Nicolas

11/27/18

11/26/18

WARNING to not submit on website too early, I s*** it up

Hi now I am really sad. I did ask the question WHEN are repos pulled, I got no official answer.

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WARNING to not submit on website too early, I s*** it up

Hi now I am really sad. I did ask the question WHEN are repos pulled, I got no official answer.

11/26/18

Abrar Jaleel, Antti Lukats2

11/26/18

Dead on Arrival

On Tuesday, 27 November 2018 04:45:02 UTC+1, Abrar Jaleel wrote: Hi, I've a different story to

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Dead on Arrival

On Tuesday, 27 November 2018 04:45:02 UTC+1, Abrar Jaleel wrote: Hi, I've a different story to

11/26/18

11/26/18

Giving up or not - engine-V story

Its 04:41 AM on Tuesday about 4 hours til deadline. As project manager I would estimate the workload

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Giving up or not - engine-V story

Its 04:41 AM on Tuesday about 4 hours til deadline. As project manager I would estimate the workload

11/26/18

11/26/18

engine-V verilator stuff pushed, maybe there are last minute hints or help for others too

Hi https://github.com/micro-FPGA/engine-V/tree/master/verilator 100% self contained install and files

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engine-V verilator stuff pushed, maybe there are last minute hints or help for others too

Hi https://github.com/micro-FPGA/engine-V/tree/master/verilator 100% self contained install and files

11/26/18

Antti Lukats, Olof Kindgren3

11/25/18

Bit Serial RISC-V

On Saturday, 24 November 2018 22:36:13 UTC+1, Olof Kindgren wrote: In terms of functionality, not

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Bit Serial RISC-V

On Saturday, 24 November 2018 22:36:13 UTC+1, Olof Kindgren wrote: In terms of functionality, not

11/25/18

Charles Papon, Antti Lukats6

11/23/18

Libero .gitignore

No worries ^^ Le vendredi 23 novembre 2018 15:43:13 UTC+1, Antti Lukats a écrit : On Friday, 23

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Libero .gitignore

No worries ^^ Le vendredi 23 novembre 2018 15:43:13 UTC+1, Antti Lukats a écrit : On Friday, 23

11/23/18

11/22/18

EZ verilator setup

Hi if you want it fast and easy: https://github.com/micro-FPGA/engine-V/tree/master/verilator/ez_test

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EZ verilator setup

Hi if you want it fast and easy: https://github.com/micro-FPGA/engine-V/tree/master/verilator/ez_test

11/22/18

Antti Lukats, … Tommy Thorn8

11/22/18

M3 Assisted Boot, C code and linker and "helping others"..

On Thursday, 22 November 2018 06:13:59 UTC+1, tommy wrote: I'm confused by something, maybe

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M3 Assisted Boot, C code and linker and "helping others"..

On Thursday, 22 November 2018 06:13:59 UTC+1, tommy wrote: I'm confused by something, maybe

11/22/18

Antti Lukats, … Olof Kindgren46

11/21/18

Smalles Design, first scoring data :)

On Wednesday, 21 November 2018 14:59:26 UTC+1, Olof Kindgren wrote: For the recode, my design called

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Smalles Design, first scoring data :)

On Wednesday, 21 November 2018 14:59:26 UTC+1, Olof Kindgren wrote: For the recode, my design called

11/21/18

Tommy Thorn, … Antti Lukats19

11/21/18

How to compile Dhrystone with the Zephyr SDK?

On Wednesday, 21 November 2018 10:33:19 UTC+1, Frank Buss wrote: On Tuesday, November 20, 2018 at 9:

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How to compile Dhrystone with the Zephyr SDK?

On Wednesday, 21 November 2018 10:33:19 UTC+1, Frank Buss wrote: On Tuesday, November 20, 2018 at 9:

11/21/18

Ryan Voo, Antti Lukats2

11/20/18

Need help with compliance tests.

Read other postings and look other entries, basically you add sigature dump to uart code, this

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Need help with compliance tests.

Read other postings and look other entries, basically you add sigature dump to uart code, this

11/20/18

Antti Lukats, … Charles Papon6

11/20/18

Rules (FAQ) update again!!!!!

I was confuded here too same as you. I think if you have one softcpu targetting 2 fpga platforms and

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Rules (FAQ) update again!!!!!

I was confuded here too same as you. I think if you have one softcpu targetting 2 fpga platforms and

11/20/18

11/20/18

QUESTION: When are github repostories fetched?

Hi I assumed that they are fetched just before deadline, but now I am not sure, could it be they are

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QUESTION: When are github repostories fetched?

Hi I assumed that they are fetched just before deadline, but now I am not sure, could it be they are

11/20/18

Eric Smith, … Frank Buss7

11/18/18

adapting Zephyr to a new platform?

And here you can see how Antti did it, with the very useful "compare" function of Github:

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adapting Zephyr to a new platform?

And here you can see how Antti did it, with the very useful "compare" function of Github:

11/18/18

Jian Zhang, … Antti Lukats13

11/18/18

how to use memory resources for IGLOO2 board?

On Saturday, 17 November 2018 20:30:42 UTC+1, BabakR wrote: Hi Jian, The eSRAM (~80KB) and eNVM (256

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how to use memory resources for IGLOO2 board?

On Saturday, 17 November 2018 20:30:42 UTC+1, BabakR wrote: Hi Jian, The eSRAM (~80KB) and eNVM (256

11/18/18

Eric Smith, Antti Lukats5

11/18/18

My first compliance test passed!

On Sun, Nov 18, 2018 at 4:12 AM Antti Lukats <antti....@gmail.com> wrote: On Sunday, 18

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My first compliance test passed!

On Sun, Nov 18, 2018 at 4:12 AM Antti Lukats <antti....@gmail.com> wrote: On Sunday, 18

11/18/18

Antti Lukats, … Eric Smith5

11/17/18

Creative board official documentation, in github

On Saturday, 17 November 2018 22:08:57 UTC+1, Eric Smith wrote: Well, I guess I'm just dumb. I

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Creative board official documentation, in github

On Saturday, 17 November 2018 22:08:57 UTC+1, Eric Smith wrote: Well, I guess I'm just dumb. I

11/17/18

Nelson Ribeiro, … Antti Lukats9

11/17/18

Newest update on the contest rules

On Saturday, 17 November 2018 04:59:20 UTC+1, tommy wrote: The contest, like all contests, could be

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Newest update on the contest rules

On Saturday, 17 November 2018 04:59:20 UTC+1, tommy wrote: The contest, like all contests, could be

11/17/18

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