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RISC-V Firmware Exchange

1–21 of 21

The purpose of this group is to facilitate collegial discussions between developers, maintainers and contributors to firmware projects for RISC-V in various market segments.

Why does this group exist?

It turns out that TG groups focusing on specifications make a poor place to discuss implementation details. It also turns out that project mailing lists, some of which are quite busy, are not a good place to reach internal consensus, ask questions or make/discuss proposals.

This group is probably more slanted towards UEFI / TianoCore EDK2 development, although discussions for other firmware are welcome - e.g. U-Boot, OpenSBI, CoreBoot, MCU firmware, embedded hypervisors, C, Rust, Zig, etc, although note that there may already be specific RISC-V mailing lists for these.

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Sep 8

edk2 RISC-V Management mode implementation

Hi all, This is a somewhat refined version of the core MM implementation we are planning to upstream.

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edk2 RISC-V Management mode implementation

Hi all, This is a somewhat refined version of the core MM implementation we are planning to upstream.

Sep 8

Dhaval Sharma, Sunil V L2

Feb 6

Adding RISE FW WG mailing list. On 05/02/25 21:58, Dhaval Sharma wrote: > Hi, > If anyone is

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Adding RISE FW WG mailing list. On 05/02/25 21:58, Dhaval Sharma wrote: > Hi, > If anyone is

Feb 6

10/15/24

Image alignment requirement

Hi All, I added a potential fix: https://github.com/tianocore/edk2/pull/6322 . It seems like .entry

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Image alignment requirement

Hi All, I added a potential fix: https://github.com/tianocore/edk2/pull/6322 . It seems like .entry

10/15/24

Dhaval Sharma, … Rafael Sene34

6/10/24

ISA string discovery for FW

On 10 Jun 2024 at 09:47:28, Rafael Sene <raf...@riscv.org> wrote: how Who* Obrigado | Thank You

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ISA string discovery for FW

On 10 Jun 2024 at 09:47:28, Rafael Sene <raf...@riscv.org> wrote: how Who* Obrigado | Thank You

6/10/24

Dhaval Sharma, … Sunil V L7

2/26/24

boot hartid information passing to UPL

Let me clarify: As discussed in the meeting we are talking about 2 items. Is there any issue if one

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boot hartid information passing to UPL

Let me clarify: As discussed in the meeting we are talking about 2 items. Is there any issue if one

2/26/24

John Chew, … Tuan Phan11

10/18/23

Review request for JH7110 SoC & StarFive VisionFive 2 EDK2 code

Hi Sunil, I have sent the patches for JH7100 SoC and VF2 to edk2-devel. Please let me know if there

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Review request for JH7110 SoC & StarFive VisionFive 2 EDK2 code

Hi Sunil, I have sent the patches for JH7100 SoC and VF2 to edk2-devel. Please let me know if there

10/18/23

10/9/23

PCDs for RISC-V features

Hi All, As we have been discussing in the past, we are planning to pass most of the CPU features

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PCDs for RISC-V features

Hi All, As we have been discussing in the past, we are planning to pass most of the CPU features

10/9/23

Li, Yong, Anup Patel4

10/3/23

Consult for Secure Monitor SBI Extension

Hi Anup, 1. I worked together with StarFive who is also working with you on the existing RPMI spec

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Consult for Secure Monitor SBI Extension

Hi Anup, 1. I worked together with StarFive who is also working with you on the existing RPMI spec

10/3/23

Warkentin, Andrei, Heinrich Schuchardt10

9/12/23

Drop C extension from RISC-V calling convention requirements?

Thanks Heinrich. Agree with you on the prudence of alignment guarantees by changing the EFIAPI

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Drop C extension from RISC-V calling convention requirements?

Thanks Heinrich. Agree with you on the prudence of alignment guarantees by changing the EFIAPI

9/12/23

li bing, … Sunil V L9

9/11/23

EDK2 on RISC-V Sophgo SG2042 platform

Hi, Thanks for the previous feedback from Sunil and Leif, we did some test and finished the third

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EDK2 on RISC-V Sophgo SG2042 platform

Hi, Thanks for the previous feedback from Sunil and Leif, we did some test and finished the third

9/11/23

Jingyu Li, … Warkentin, Andrei7

9/10/23

MMU & Cache Coherence in EDK2

Hi Andrei, Answers to your questions: On Sunday, September 10, 2023 at 5:25:15 AM UTC+8 andrei.w...@

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MMU & Cache Coherence in EDK2

Hi Andrei, Answers to your questions: On Sunday, September 10, 2023 at 5:25:15 AM UTC+8 andrei.w...@

9/10/23

Dhaval Sharma, … Sunil V L20

9/1/23

Assumption about Timer freq In EDK2

Hi Sunil, I am implementing DT parser logic in the lines of your SSTC implementation for Timer lib we

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Assumption about Timer freq In EDK2

Hi Sunil, I am implementing DT parser logic in the lines of your SSTC implementation for Timer lib we

9/1/23

John Chew, Tuan Phan10

8/23/23

How to dispatch DXE in 32-bit address in PEI-less flow ?

Hi Tuan, Thanks for the PCIe example. It works that way. Alternatively, allocating all "

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How to dispatch DXE in 32-bit address in PEI-less flow ?

Hi Tuan, Thanks for the PCIe example. It works that way. Alternatively, allocating all "

8/23/23

Tuan Phan, … Li, Yong7

8/16/23

StandaloneMm updates and need feedback

Hi Dhaval, Thanks so much for the feedback, will reply your comments ! >There is probably some

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StandaloneMm updates and need feedback

Hi Dhaval, Thanks so much for the feedback, will reply your comments ! >There is probably some

8/16/23

li bing, … Tuan Phan6

8/16/23

Questions about configuring RISC-V MMU

You need to check whether AMOArithmetic PMA enabled for the failing region(0x7FFFF3D10). Refer to

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Questions about configuring RISC-V MMU

You need to check whether AMOArithmetic PMA enabled for the failing region(0x7FFFF3D10). Refer to

8/16/23

Warkentin, Andrei, … Dhaval Sharma15

8/9/23

EFI_RISCV_FIRMWARE_CONTEXT

I better hurry up with those patches for review (at least for RiscVVirt). A From: Dhaval Sharma <

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EFI_RISCV_FIRMWARE_CONTEXT

I better hurry up with those patches for review (at least for RiscVVirt). A From: Dhaval Sharma <

8/9/23

John Chew, … Tuan Phan5

8/2/23

PEI-less flow dispatch DXE twice in VF2

Hi Yong/John, I am seeing some issues based on your writing. Not that this is my observation QEMU

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PEI-less flow dispatch DXE twice in VF2

Hi Yong/John, I am seeing some issues based on your writing. Not that this is my observation QEMU

8/2/23

Warkentin, Andrei, … Heinrich Schuchardt9

6/28/23

Clang builds of Tiano?

On 6/28/23 16:51, Sunil VL wrote: > On Wed, Jun 28, 2023 at 02:46:31PM +0200, Heinrich Schuchardt

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Clang builds of Tiano?

On 6/28/23 16:51, Sunil VL wrote: > On Wed, Jun 28, 2023 at 02:46:31PM +0200, Heinrich Schuchardt

6/28/23

Warkentin, Andrei, Tuan Phan3

5/1/23

Backtraces in UEFI

I would suggest a compiler option to guarantee stack frame compliance. It's not a reasonable

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Backtraces in UEFI

I would suggest a compiler option to guarantee stack frame compliance. It's not a reasonable

5/1/23

Sunil V L, Rafael Sene3

4/3/23

Obsolete riscv-edk2/riscv-edk2-platforms repos?

Sure Rafael. If I don't see an objection, I will request via he...@riscv.org Thanks! Sunil On 03/

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Obsolete riscv-edk2/riscv-edk2-platforms repos?

Sure Rafael. If I don't see an objection, I will request via he...@riscv.org Thanks! Sunil On 03/

4/3/23

3/23/23

Hello everyone, Yong from Intel joined. Thanks

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Hello everyone, Yong from Intel joined. Thanks

3/23/23

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