[RISC-V][Devboards Program] October 1st, Devboards Program, 2026

[Greg Sterling]

Our next meeting will be tomorrow.  Local times can be found by logging into LFX at https://lfx.linuxfoundation.org/tools/ or going to the Tech Meetings calendar at https://riscv.github.io/riscv-tech-calendar/.

The agenda will focus on standard topics:

• Program updates from RISC-V
• Board and Project updates
• Future Board Program Discussion
• What's cool?
  
• Misc Notes

Any topics, updates, or information can as always either be raised at the beginning of the meeting or added to our agenda document, Dev Board Group Minutes (moved back to Google Docs).  Please note we have migrated away from the Confluence for meeting minutes.  Please reach out if you have any issues viewing the meeting minutes.

Thanks, and I look forward to seeing you tomorrow!

Greg Sterling (RISC-V International)

[Greg Sterling]

Thanks everyone for another great meeting.  Here are the meeting minutes.

Greg Sterling (RISC-V International)

Board Updates & Information

SiFive BigSky RISC-V CPU Complex + AMD ROCm Demo

• YouTube demo of BigSky 

SiFive BigSky RISC-V CPU Complex + NVIDIA CUDA Demo

• YouTube demo of BigSky with nVidia 

Efinix Announces New Sapphire RV64 SoC, Bringing 64-Bit RISC-V Performance to Embedded FPGA Designs (also link) 

• Built on the RISC-V Instruction Set Architecture (ISA), Sapphire RV64 is designed for customers whose applications have outgrown the performance, memory, cache, and I/O limits of 32-bit embedded cores but still need the flexibility and low-power capabilities of an FPGA.

Oreboot, U-Boot, & Firmware

Beyond the Legacy: Embracing UEFI Platform Firmware 

Operating Systems

Xen on RISC-V boots on the Spacemit K3: our first RVA23 board!

• Oleksii Kurochko and Baptiste Le Duc report on Xen’s RISC-V port, covering both dom0less deployments and Dom0 with the xl toolstack. The session reviews upstream and downstream progress, hardware requirements, remaining gaps and the roadmap, with a live demonstration. 

Development

RISC-V ISA Explorer

• Tech Preview for the ISA explorer.

RVVTS: Open-Source RTL Bug Hunting for Complex RISC-V ISA Extensions (Manfred Schlägl)  

• RISC-V ISA extensions such as Vector introduce large configuration spaces and subtle corner cases that make RTL verification and debugging increasingly challenging.

sifiveinc/skl: SiFive Kernel Library · GitHub

• The SiFive Kernel Library (SKL, pronounced "skill") is an open-source collection of high performance routines, referred to as kernels, that provide a drop-in replacement for performance-critical components of machine learning (ML) and artifcial intelligence (AI) workloads running on SiFive or other RISC-V-based vector CPUs. 

Episode 1: From Teaching Core to DOOM: How We Built a RISC-V Gaming System - YouTube

• In this RISC-V Builders session, Tobias Scheipel (Asst. Professor at Graz University of Technology) and Bernd Stelzl (Master’s Student in Computer Science at Graz University of Technology) discuss how HaDes-V grew from a teaching core into a complete RV32IM system with DDR memory, graphics, keyboard input, audio, and enough performance to make DOOM playable. Along the way, they share the engineering challenges, design decisions, and lessons learned from pushing a small RISC-V platform far beyond its original purpose. 

What’s Cool

[2608.28076] Performance Evaluation of Fast Fourier Transforms on Emerging RISC-V Hardware with Vector Extension Support

• 
  

P Extension v0.6 — Development Milestone Approved

• The Packed SIMD Task Group approved the Development Milestone on 2026-09-28 with 7 of 9 eligible voting companies casting a ballot, quorum 5, and a split of 6 approve, 0 object, 1 abstain.  

Zamlet - An in-progress exploratory RISC-V VPU (Ben Reynwar)

• An exploratory RISC-V VPU that scales to very large number of lanes. 

Aheesa Advances India’s Semiconductor Ambitions with Indigenous VIHAAN Broadband Networking Chip | Machine Maker - Latest Manufacturing News

• Aheesa Digital Innovations has reached a significant milestone in India’s semiconductor journey with the development of the VIHAAN series, a homegrown broadband access System-on-Chip (SoC) built on the open-standard RISC-V architecture. The achievement comes as the Chennai-based fabless semiconductor company completes five years of operations and prepares for its next phase of commercialization. 

Community Motion: What Are RISC-V Advocates Doing?

• A summary of what some of the RISC-V Advocates have been up to in the community. 

Xcena Cuts Data Movement to Address Memory Bottlenecks - EE Times

• Processing data closer to memory is not a new idea, but South Korean startup Xcena believes it has a better way to do it by leveraging the Compute Express Link (CXL) protocol. 

Hackaday Europe 2026: Fluid Kernels And Optimizing C++ For MCUs

• A technical proposal from Hackaday Europe detailed "Fluid Kernels"—a hybrid design bridging lightweight RTOS efficiency with MPU-isolated process crash resilience for RISC-V MCUs.

Miscellaneous Notes

RISC-V Weekly Report (2026-09-21

• A lot of interesting notes

Eswin edges toward the first RISC-V listing in Hong Kong

• Eswin cleared the vetting stage at the Hong Kong exchange this week, according to DigiTimes.  

BitNetMCU: High Accuracy Low-Bit Quantized Neural Networks on a low-end Microcontroller

• The BitNetMCU framework introduced optimization passes achieving over 99% accuracy using 1-bit/ternary weights on low-cost 32-bit RISC-V microcontrollers.