[RISC-V][Devboards Program] July 16, Devboards Program, 2026 - US East-friendly

[Greg Sterling]

Our next meeting will be tomorrow.  Local times can be found by logging into LFX at https://lfx.linuxfoundation.org/tools/ or going to the Tech Meetings calendar at https://tech.riscv.org/calendar/.

The agenda will focus on standard topics:

• Program updates from RISC-V
• Board and Project updates
• Future Board Program Discussion
• What's cool?
  
• Misc Notes

Any topics, updates, or information can as always either be raised at the beginning of the meeting or added to our agenda document, Dev Board Group Minutes (moved back to Google Docs).  Please note we have migrated away from the Confluence for meeting minutes.  Please reach out if you have any issues viewing the meeting minutes.

Thanks, and I look forward to seeing you tomorrow!

Greg Sterling (RISC-V International)

[Greg Sterling]

We had another great Dev Boards meeting last week.  Here are the meeting minutes for those who are interested.

Greg Sterling (RISC-V International)

Board Updates & Information

[youtube] Xuantie C950 Core

[youtube] ARBEL Server-CLass RISC-V CPU

[phoronix] RVV Performance Benchmarks with K3 SoC

[allaboutcircuits] Efinix Seeks to Overcome Edge AI Constraints With New FPGA Family

• The new devices sit inside the broader Titanium FPGA lineup, but they are not just another density expansion, according to the company. Titanium Edge is aimed at the more specific problem of how to bring FPGA based acceleration into edge AI systems where power, space, security, and reliability all matter at the same time.

Taobao k3 cluster is now available for sale.

Hardware Developments

[riscv] Think Silicon Demonstrates NEOX G-Series RISC-V GPU Running Vulkan 1.3

• Open-standard graphics hardware is the missing link for RISC-V consumer devices; native Vulkan support on an open-ISA GPU reduces dependency on proprietary, closed-source GPU IP from Imagination or ARM Mali.

[theregister] Homebrew GPU Using 8,192 RISC-V Chips [tomshardware]

• Demonstrates to the hardware community that because RISC-V has no licensing restrictions, developers can aggressively tile thousands of independent cores together to construct highly parallelized, custom compute accelerators (like a homebrew GPU or an AI matrix engine) completely from scratch.

Oreboot, U-Boot, & Firmware

[theregister] RISC-V firmware project wants every board booting from the same hymn sheet

[qsoe] Harmonic Firmware Initiative (HFI)

• Aims to create, standardize, and maintain firmware for RISC-V systems.

Sg2044 has EDK2 with MultiArchUefiPkg

Operating Systems

[techveda] RISC-V Embedded Linux: What's Real, What's Not

• For companies looking to migrate from ARM to RISC-V, this highlights that although prototyping and single-purpose applications are ready today, mainstream consumer devices still face a steep firmware and software stabilization hurdle.

[Fedora] FVF is building Fedora 45 on RVA23

[Fedora] Fedora 44 Image can run on SpaceMIT server directly

Imagination PowerVR BXM-4-64 GPU Firmware Upstreamed For The T-Head TH1520 - Phoronix

Secureboot https://github.com/rhboot/shim/pull/778

Development

[amazon] Virtual Prototyping with MachineWare's SIM-V on AWS

• "Shifting left" on software development resolves the massive time-to-market bottleneck associated with new hardware, enabling developers to build and optimize their software stack concurrently with silicon design.

[youtube] LFNW 2026: Clonezilla Live on RISC-V (pt2): From Porting to Mass Deployment

[reddit] RISCstar Toolchain for RISC-V

• Maintaining cross-distribution toolchain compatibility is complex; this release raises the baseline glibc requirements (e.g., Ubuntu 24.04 LTS for native RISC-V hosts), aligning modern compilers directly with the enterprise Linux ecosystem.

[reddit] Introduction to RISC-V - Processor Design From Overview to Assembly Language

What’s Cool

[tbsnews] Buet develops open-source 32-bit RISC-V processor - The Business Standard [daily-sun]

• This represents a major milestone in regional semiconductor sovereignty, proving that academic institutions can leverage open-source electronic design automation (EDA) tools and international foundry programs to design and manufacture functional microprocessors.

[design-reuse] RISC-V Accelerates Physical AI Chips

• Unlike cloud-based data centers, edge-based Physical AI needs deep, low-latency integration between software and custom silicon, making RISC-V's open-standard, highly modular ISA a highly attractive design alternative.

[riscv] RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses

• This highlights the immense potential of parallel RISC-V architectures to handle continuous signal processing and heavy AI inference in tiny, energy-efficient, and privacy-preserving wearable form factors.

[reddit] DIY RISC-V Ultracluster

• Hobbyist cluster projects like this act as crucial environments for testing distributed networking software, decentralized load balancing, and Kubernetes configurations over non-x86 infrastructure.

[amazon] RISC-V System-on-Chip Design

• RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.

Events (RISC-V Calendar)

[aifoundry] CORE-ET Hackathon

• RISC-V Hackathon with the purpose of porting AI models to a open-source RISC-V accelerator.

1. AI Infra Summit – RISC-V Pavilion

• Date: September 15 – September 17, 2026

• Location: Santa Clara Convention Center, California, USA

• What it’s for: RISC-V International is hosting a dedicated "RISC-V Pavilion" (Booth 900) alongside ecosystem leaders like Akeana. The event centers on enterprise full-stack AI Infrastructure, focusing heavily on how open-source silicon can scale up to meet cloud-level AI workloads and data center orchestration demands.

• Official Event Link: RISC-V Calendar

2. CARLA 2026 (Latin American High Performance Computing Conference)

• Date: September 21 – September 25, 2026

• Location: Universidad Nacional de Córdoba, Córdoba, Argentina

• What it’s for: CARLA is Latin America's premier hub for High-Performance Computing (HPC) and large-scale AI infrastructure. The RISC-V steering committee is closely involved this year, as academic and regional research labs increasingly rely on the royalty-free ISA to run high-density cloud, parallel processing, and supercomputing clusters.

• Official Event Link: HPC Cineca Event Portal or check the RISC-V Calendar Listing.

3. Open Source Summit Europe

• Date: October 7 – October 9, 2026

• Location: Prague Congress Centre, Prague, Czech Republic

• What it’s for: Operated by the Linux Foundation, this massive developer gather-point features major tracks on the RISC-V software ecosystem. Industry discussion will focus heavily on upstream operating system porting (Debian, Ubuntu, SUSE), standardizing boot toolchains, and ensuring cloud-native container tools run flawlessly on native RISC-V hardware hosts.

• Official Event Link: Linux Foundation Events

4. RISC-V Summit China (6th Annual)

• Date: October 18 – October 20, 2026

• Location: Shenzhen Convention & Exhibition Center, Shenzhen, China

• What it’s for: China is the global epicentre for commercial and high-volume RISC-V deployments. This major annual summit attracts over 3,600 industry insiders to launch new microcontrollers, single-board computers (SBCs), and custom server-class System-on-Chips (SoCs). It's the primary window for viewing near-term hardware consumer trends.

• Official Event Link: RISC-V Summit China Home

Froscon Germany

Miscellaneous

[eetimes] RISC-V Is Inevitable, State of the Union Keynote Argues

[youtube] State of the Union | Krste Asanovic