Attendees: Jeff, Thea, Yu Bo, Wei Fu, Daniel, Chen Wang (AOSP), Darren (SUSE)
None
Program Updates:
Debian
Aurel32 removed all qemu builder to use new Unmatched boards (13)
No update about official port (Waiting FTP team to add riscv64 to unstable)
Fedora
Working hard on Sophgo support (milkv)
Desktop support looking good, especially with with LibreOffice
Development board announced at T-HEAD event
Interested in having DevBoard program
TH1520 support being added as well for T-Head-Light board
Imaging work underway for both boards
SUSE
Experimental contrib project for some Allwinner D1 boards: Nezha, LicheeRV x 2 and MangoPi MQ-Pro.
https://build.opensuse.org/project/show/devel:RISCV:Factory:Contrib:AllwinnerD1
Canonical (Heinrich via email because he’s at Embedded World in Nürnberg)
With the Ubuntu 22.04.2 release we have the following changes:
an image is provided for the Microchip PolarFire Icicle Kit
the LicheeRV board is now additionally supported in the Ubuntu Jammy LTS release.
The full overview of available RISC-V Ubuntu images is available at https://ubuntu.com/download/risc-v.
Android (AOSP)
Google is Landing ART patches for switch interpreter: almost done
Google will upstream T-Head’s patches in AOSP/ART and later separate into standalone repo. Cao Xia (from ESWIN) sent an alternative patch https://r.android.com/2457968, but Google wants to proceed with T-Head’s work as they have a full compiler implementation based on that.
oreboot
Initial support for JH7110 / VisionFive 2 in a PR; now 4th RISC-V platform
Yes, Daniel just bought himself one of those boards and it arrived quickly
Would like a Pine64 Star64 as well 🙋
Got serial output so far
Created an XMODEM loader for it in Rust 🦀
It could be run on the web if someone put the effort into it
DRAM init started; porting code from StarFive’s U-Boot fork as reference code
StarFive have now published a preliminary PDF https://doc-en.rvspace.org/JH7110/PDF/JH7110_TRM_StarFive_Preliminary.pdf getting us some understanding of the JH7100 retrospectively (GPIOs, PLLs, clocks…)
RISC-V
February monthly status continues to look good (link). Awaiting new projects.
ROMA
No update
VisionFive V1s
Final 7 boards being prepared for shipment
ICE-V
First round of evals sent – accepts/rejects
14 of 20 boards requested for shipment
Form remains open for remaining boards.
VisionFive V2s
Approval to order 80 boards
60 boards spoken for. Geographic breakdown understood.
Expect to place orders with Allnet week of 3/13.
VF2 upstream plan https://rvspace.org/en/project/JH7110_Upstream_Plan
Active work underway to improve the RISC-V Compatible Trademark Permission Process
See “Branding Guidelines” for program details
Details about the work are available on the sig-arch-test list. Please join there if interested or reach out to Jeff.
Google Sites draft created for program information
Jeff will start a discussion thread on the list
What’s cool?:
https://www.investorsobserver.com/news/qm-pr/4753293415472000 - RISC-V MIPS (eVocore P8700) processor getting award at Embedded World
https://liliputing.com/asus-tinker-v-is-the-companys-first-single-board-pc-with-a-risc-v-chip/ - Asus and Renesas getting into dev boards
https://semiengineering.com/what-makes-risc-v-verification-unique/ - Discussion about complexities of building (and verifying) an SOC
https://www.eenewseurope.com/en/plumerai-ports-people-detection-ai-to-espressif-esp32-s3/ - (last sentence) Plumerai is moving all future microcontrollers to RISC-V.
https://milkv.io/ - server being brought up by Fedora now
Lots of Embedded World activity this week!!!
Daniel has held a real Tinker V in his own hands 🙂