Board Updates:
None
Program Updates:
Debian
oreboot
We are reducing the JH7100 boot flow to one single stage before payload
Our default payload is LinuxBoot ( https://linuxboot.org )
We offer non-SBI booting to support holistic operating systems, research initiatives and other bare metal apps
Just did a case study on the feasibility of translating the DRAM init C code to Rust 🦀
There are roughly 500 writes of magic values to magic registers 🧚
It will be just a matter of some time and testing 🥳
Firmware
Daniel is looking into SBoM implementations for inclusion in firmware, evaluating
SwID, specifically uswid (rather simple, also being evaluated in coreboot and LVFS)
CycloneDX (an OWASP project, very mature); just joined their Slack and discussions on GitHub
Gave a talk last Sunday touching the issue https://metaspora.org/fiedka-firmware-analysis-and-modding.pdf and before at OSFC https://metaspora.org/firmware-sbom-annotations-audits.pdf
RISC-V (Jeff)
Overview of RISC-V Exchange
Add items at the the “Submit an items” yellow button: link
RISC-V Summit gathering during Members Day
Will post details when confirmed
October project status collected
Program Summary slides created and shared with RISC-V execs
Project review (Developer Boards Details webpage)
ICE-V Program started (website)
Purchased 20 boards
Form solicitation ends Nov. 15 (1 submission so far)
Likely need to partner with Academic Partners to fill projects
What’s cool?:
New SiFive processors for Wearables and Consumer Products (P670 & P470): https://www.sifive.com/press/sifives-new-high-performance-processors-offer-a-significant
RISC-V makes Maker Shed cover: https://www.makershed.com/products/make-magazine-volume-83-print
RISC-V Hackathon in India (VEGA processor): https://twitter.com/VegaProcessor/status/1589511270654705664
Sipeed MAIX M1s (AIoT, BL808, C906 + 2 RV32 cores) and M0sense (BL702) IGG: https://www.indiegogo.com/projects/sipeed-maix-new-experience-to-risc-v-aiot-tinyml
Chromite RISC-V core generator: https://chromite.readthedocs.io/en/latest/overview.html
LibreOffice Enables RISC-V 64-bit Support: https://www.phoronix.com/news/LibreOffice-RISC-V-64-bit-Build
2022 RT-Thread Developer Conference: https://twitter.com/rt_thread/status/1592081855054217217
Alibaba C908 Announce (Vector 1.0, Bitmanip 1.0, CMO, ePMP, Svinval, Sv48): https://riscv.org/blog/2022/11/xuantie-c908-high-performance-risc-v-processor-catered-to-aiot-industry-chang-liu-alibaba-cloud/
Pine64 update: https://www.pine64.org/2022/11/15/november-update-tuned-in/
RISC v. RISC-V v. ARM: https://www.makeuseof.com/risc-vs-arm-what-is-the-difference/
Miscellaneous notes:
Thea’s proposed we build our own dev board…interesting idea for January.
December meetings (both) will be canceled due to conflicts (personal and Summit)