[RISC-V][Devboards Program] August 6, Devboards Program, 2026
Greg Sterling
| Our next meeting will be tomorrow. Local times can be found by logging into LFX at https://lfx.linuxfoundation.org/tools/ or going to the Tech Meetings calendar at https://tech.riscv.org/calendar/. |
Greg Sterling
Board Updates & Information
K3 Is a Compelling Board, But Difficult to Buy
Banana Pi made full firmware and carrier board documentation available for the BPI-SM10 developer kit, housing a SpacemiT K3 module in an Nvidia Jetson Orin Nano pin-compatible form factor.
XiangShan Published Revision to Kunminghu V3 Core
The open-source XiangShan project published design revisions for its Kunminghu v3 out-of-order core, targeting Sapphire Rapids-class instruction throughput and featuring an overhauled RVV vector pipeline.
Andes teaches its RISC-V edge platform to speak transformer – Jon Peddie Research
Andes has upgraded its AndesAIRA AnDLA I370 accelerator and neural network software stack to support Vision Transformers, vision-language models, and small language models at the edge.
[X] SiFive P870-D is ideal for datacenter infrastructure applications
[reddit] GeekBench 7.0.0 is available. Some RISC-V Results
Espressif ESP32-C61-MINI-1/1U Wi-Fi 6 and BLE IoT module launched for about $2 - CNX Software
Defcon badge using RISC-V BaoChip : https://defcon.social/@defcon/117015518239738951
5 More Popular SBCs for July 2026
Orange Pi 6 Plus
Radxa Orion 06N
AAEON de next-RAP8
Cubie A7Z
Geniatech XPI-7110 (RISC-V)
Make it 6, although I don’t know if this is an SBC. We just saw a demo of YA 1000 core RV board at FMS yesterday. Saw it there last year as well but it was not in general production yet….
You may know the tortured history of the Kilocore RV SoC. I think it started at MIT as a grad student project with Quan Nguyen (who had just graduated from Berkeley)
https://www.csail.mit.edu/research/t-1000-thousand-core-coherent-shared-memory-system
Not sure why he abandoned it… started working on something else.
https://www.youtube.com/watch?v=0u1D2UBzzrI
A RISC-V cluster server optimized for AI and high-performance workloads, featuring a standard 2U 19-inch rack form factor and 48 SpacemiT K3 chips。• It delivers 768-core native RISC-V computing power and 2880 TOPS general AI compute, supporting 80B-parameter MoE models and 8–16 concurrent AI inference tasks.
Oreboot, U-Boot, & Firmware
The U-Boot 2026.07 release added mainline boot support for modern RVA23 SoC families, expanded StarFive JH7110 SPI flash routines, and standardized device tree bindings for OpenSBI hands-off.
Updated Yocto support for SiFive RISC-V platforms.
Embedded firmware consultancy Bootlin released an LTS update for the SiFive Yocto BSP layers (meta-sifive and freedom-u-sdk), packaging OpenSBI 1.8+, U-Boot 2026.07, and recent Linux kernels for HiFive Unleashed and Unmatched hardware.
riscv: Add supervisor pointer masking infrastructure [LWN.net]
A kernel patch series introduced the lifecycle logic for Supervisor Pointer Masking (Sspm), utilizing the SBI 3.0 Firmware Features (FWFT) interface to configure pointer tagging across all online HARTs during boot and CPU hotplug transitions.
riscv: add SBI Supervisor Software Events support [LWN.net]
An upstream patch series refined Linux SBI Supervisor Software Events (SSE) support to provide an out-of-band firmware-to-supervisor event delivery path, enabling hardware error logging (RAS/RERI) and PMU overflow handling without relying on standard interrupt lines.
Operating Systems
riscv: Add reliable stack unwinding for livepatch [LWN.net].
A patch series submitted to the Linux kernel added explicit frame-record metadata, ftrace frame pointer preservation, and a frame-pointer unwinder for riscv64.
riscv: Introduce support for hardware break/watchpoints [LWN.net]
Himanshu Chauhan published v6 of the kernel patch set integrating the RISC-V Sdtrig debug extension into the kernel perf subsystem alongside new ptrace interfaces (NT_RISCV_HW_BREAK/WATCH).
Implement Eager Page Splitting for RISC-V [LWN.net]
KVM developers added Eager Page Splitting to the RISC-V port, enabling huge pages to be split in ioctl context during dirty logging rather than triggering guest vCPU page faults.
riscv: Add reliable stack unwinding for livepatch [LWN.net]
The upstream Linux kernel (7.2-rc series) added explicit frame-record metadata, frame-pointer preservation in dynamic ftrace, and a conservative unwinder for riscv64 to support kernel livepatching.
NetBSD 11.0 released [LWN.net]
The NetBSD project released version 11.0, featuring an official port to RISC-V alongside enhanced Linux binary compatibility (compat_linux) and NPF firewall updates.
Development
Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW
Researchers open-sourced a workflow utilizing the RISC-V Unified Database (UDB) and LLM-driven MCP agents to remap legacy non-compliant custom instruction sets into ratified spaces automatically.
Pushing the limits of RISC-V emulation | Ayush Shukla (thread)
Architectural research published practical compilation methodologies combining Clang's preserve_none calling convention with basic-block tail calls to achieve near-native execution speed during RISC-V emulation.
Kernel & Embedded News: Linux 7.2 Nears Release
Upstream kernel testing confirmed target cross-compiler requirements for Linux 7.2 RISC-V builds, enforcing GCC 15.2+, Binutils 2.46, and LLVM/Clang 21+.
[reddit] Upstream Progress Update
Upstream progress for SpacemiT K1/K3
RISC-V Mentorship project ports AudioMark to RISC-V
GNU Binutils 2.47 Released With More RISC-V Extensions, New Options - Phoronix
GNU Binutils 2.47 was officially released, featuring expanded assembler and linker support for new standard RISC-V ISA extensions and improved reproducible build tooling targeting Linux distributions like Fedora and Debian.
Delivers critical low-level toolchain infrastructure required for general-purpose Linux distributions to build optimized binary packages using modern RISC-V profiles.
WebAssembly Micro Runtime Expands RISC-V Android & Sandbox Runtime Support
The Bytecode Alliance updated the WebAssembly Micro Runtime (WAMR) with optimized Ahead-of-Time (AOT) and JIT execution engines for riscv64 and riscv32 targets across Android, Linux, and embedded environments.
Build a RISC-V Toolchain: GCC and LLVM | Luca Berton
LLVM maintainers merged critical backend patches targeting the upcoming LLVM 21 toolchain cycle, enhancing auto-vectorization heuristics for RISC-V Vector (RVV 1.0) and adding support for vendor-specific matrix extensions.
What’s Cool
The New Defcon Badges Pack a Unique Open Source Chip That Doubles as a Security Key | WIRED
RISC-V Enabled Badge Offers Open & Transparent Security Implementation.
What It Takes to Build an AI Chip Startup in Europe - EE Times Podcast
An interview with Fabrizio Del Maffeo of Axelera to discuss scaling a European semiconductor startup, and challenges that come with raising capital to deliver Edge AI and models on RISC-V.
Openchip Introduces BER10 RISC-V Chip Built for AI, HPC and Critical Infrastructure - HPCwire
ESP32-S31 now in mass production and available for purchase
Designed for next-generation AIoT applications, ESP32-S31 is a high-performance dual-core RISC-V SoC with comprehensive wireless connectivity, making it ideal for smart home hubs, smart speakers, edge AI devices, industrial automation, and more.
Porting SIMD to RISC-V Vectors
ESP-KVM - An open-source IP KVM solution based on ESP32-P4 RISC-V MCU - CNX Software
RISE RISC-V Runners offer free, native RISC-V CI on GitHub
The RISC-V Software Ecosystem (RISE) project rolled out native GitHub Actions runners on physical RISC-V hardware (ubuntu-24.04-riscv), eliminating QEMU emulation overhead for open-source CI/CD workflows.
[YouTube] He Built the Instruction Set that Billions of Chips Now Run On
The open standard that quietly changed everything. In this episode of the Semiconductor Leadership Podcast, host Salah Nasri sits down with Krste Asanovic, Co-founder and Chief Architect of SiFive, to talk about how RISC-V went from a Berkeley lab tool to billions of shipped chips and why the biggest force driving its adoption has nothing to do with technical superiority.
RISC-V International
K3 Boards
OSU/OSL has received 5x 16gb K3 boards that will be brought online.
Awaiting confirmation from PLCT for their 5x 16gb K3 board order.
Expecting shipment for 32gb K3 to Ecosystem Lab Partners in the next two weeks.
Miscellaneous Notes
Notes on cooling the SpacemiT K3 systems:
PicoITX has the best cooling from Carl’s testing. The thermal paste used is terrible, highly recommend pulling the cooler and replacing the thermal compound with something like Thermal Grizzly Kryonaut or Arctic Silver V for the SoC. The thermal pads for the DRAM seem to be fine, but the thermal pad for the eMMC/UFS seems to be too short but doesn’t seem to be an issue.
The CoM260 modules are a mess from a cooling perspective. The same thermal paste issues as the PicoITX, replacement of the thermal paste is recommended. However, the Z heights of various components on the module board and the heatsink is a mess. You can use thermal paste on the inductors (highest Z height) but then the SoC is too low from the heatsink to make contact. Using a 1mm Thermal Pad is too thick and can damage the board. Using thermal paste works, but you need so much of it. I am going to try a 0.5mm pad in the near future. There are also pads needed for the DRAM and NAND and the same problems exist around z-height. Carl will report back with more info once some more testing is done.
Events (RISC-V Calendar)
COSCUP & UbuCon Asia - DeepComputing
August 8-9 at Taipei, China
Organizers announced dedicated technical sessions for COSCUP & UbuCon Asia 2026 in Taipei, Taiwan, covering native RISC-V Linux desktop applications, edge AI toolchains, and hardware enablement.
October 19-20 at Raleigh, North Carolina
All Things Open is a polyglot technology conference focusing on the tools, processes and people making open source possible.
August 15-16, Germany