[RISC-V][Devboards Program] October 16, 2025 - West-friendly

[Greg Sterling]

Our next meeting will be tomorrow, October 16th, 2025.  Local times can be found by logging into LFX at https://lfx.linuxfoundation.org/tools/ or going to the Tech Meetings calendar at https://tech.riscv.org/calendar/.

The agenda will focus on standard topics:

• Program updates from RISC-V
• Board and Project updates
• Future Board Program Discussion
• What's cool? (time permitting)
  

Any topics, updates, or information can as always either be raised at the beginning of the meeting or by adding it to our agenda document, Dev Board Group Minutes.  Please note we have migrated to Confluence for meeting minutes.  Please reach out if you have any issues viewing the meeting minutes.

Thanks, and I look forward to seeing you tomorrow!

Greg Sterling (RISC-V International)

[Greg Sterling]

Thanks everyone for another great meeting!  Meeting minutes are posted below.

Greg Sterling (RISC-V International)

Notes & Action Items

Board Updates:

·       Beagle, SiFive, StarFive, RIOS, Allwinner, Microchip, SpacemIT, Milk-V

·       https://finance.yahoo.com/news/upbeat-technology-sifive-introduce-next-120500586.html?guccounter=1&guce_referrer=aHR0cHM6Ly93d3cuZ29vZ2xlLmNvbS8&guce_referrer_sig=AQAAACOCiwmvP8J-g_7VnVHgCnxRj2vN3rtWG8akwAEYeIUMCYAeNhZ4K3PXZ0EQ2Ay-CqmI_WvEKl5uRo9QG90uOHtD-0FCubatFoYR44jNA9V3lc5VkpT7rZe05SCbSsqF7kr-mJ0LEB50xI5X9oi2vWwAHnwWvmX9amu2cmt6zMGv

o   UP201/UP301 family MCU merges dual-core RISC-V and AI acceleration for breakthrough efficiency, intelligence, and battery life—live demos at RISC-V Summit

·       https://semiwiki.com/forum/threads/sifive-announces-new-high%E2%80%91performance-risc%E2%80%91v-datacenter-processor-for-demanding-ai-workloads.23811/

·       https://www.androidpimp.com/embedded/orange-pi-rv2-plus/

o   Wireless updated to Wi-Fi 6

·       https://linuxgizmos.com/terasic-announces-starter-kit-featuring-risc-v-nios-v-processor-and-software-bundle/

o   RISC-V Soft-Core

·       SiFive Unmatched runs with upstream linux kernels now

Program Updates:

·       oreboot

·       U-Boot

·       Firmware

·       Operating Systems

o   BSD - FreeBSD, NetBSD

•  

o   Linux - AlmaLinux, Arch Linux, Alpine Linux, Debian, Fedora, SUSE, Canonical, OpenEuler, NixOS

§  SUSE annual Hack Week (December) https://hackweek.opensuse.org

§  There are a couple of RISC-V projects that people can join

§  Welcome to join existing projects people are planning

§  Open to the world

§  Hackweek Project: https://hackweek.opensuse.org/25/projects/create-opensuse-images-for-arm-slash-risc-v-boards

§  CFI changes did not make it into the kernel, and needs to be reworked

o   Other - seL4, Android AOSP, Managarm

•  

·       Images

o   Development - Gentoo, FedoraVForce (Mirror US)

·       Compilers

·       CI/CD

·       RISC-V International

o   NA Summit - registration, schedule

•  

o   Developer Board Status: Monthly Status Report, Final Status Report

o   Dev Boards Applications

§  Milk-V Megrez

§  ESWIN EBC77

§  Banana Pi F3

§  Orange Pi RV2

What’s cool?:

·       https://www.newelectronics.co.uk/content/blogs/risc-v-international-to-announce-25-market-penetration

·       https://www.reddit.com/r/RISCV/comments/1o7lcvb/ubuntu_2510_container_runs_on_orange_pi_rv2/

o   Unclear how this has been modified to get it working

·       Box64 v0.3.8 Released https://github.com/ptitSeb/box64/releases/tag/v0.3.8

o   Implemented more AVX instructions for RISC-V. Scalar only (so at least more software functions)

o   Has implemented a caching system, after running stores on the disk to enhance running

·       Tenstorrent Ascalon FPGA instruction throughput including RVV: https://camel-cdr.github.io/rvv-bench-results/tt_asc_x/index.html (From three weeks ago)

·       Tenstorrent updated ocelot/bobcat getting it closer to full RVV 1.0 adding segmented load/store support and division is WIP: https://github.com/tenstorrent/riscv-ocelot/blob/bobtail/feature/ms4_div/docs/Bobtail-Final-Presentation.pdf

·       Google Coral open sourced: https://github.com/google-coral/coralnpu (RV32IMF_Zve32x + custom matrix, NPU)

·       Charly Castes (Mothy et al) introduced Miralis at SOSP http://miralis-firmware.github.io/docs/introduction - a runtime to wrap an M-mode runtime, for audits and sandboxing; paper: https://infoscience.epfl.ch/entities/publication/64497ab4-c352-43b4-9858-d25abb7b017e

·       https://arxiv.org/abs/2504.08334#:~:text=Implemented%20on%20FPGA%20with%20Chisel,and%20efficiency%20of%20vector%20processors

·       Article featuring Yuning Liang’s talk from OSS in Amsterdam https://semiwiki.com/ip/risc-v/361890-yuning-liangs-painstaking-push-to-make-the-risc-v-pc-a-reality/and the general development of RISC-V AI hardware

Miscellaneous notes:

·       RISCover: Automatic Discovery of User-exploitable Architectural

Security Vulnerabilities in Closed-Source RISC-V CPUs: https://ghostwriteattack.com/riscover_ccs25.pdf

o   sandsifter: x86 processor fuzzer - https://github.com/Battelle/sandsifter

o   Breaking the x86 ISA - https://www.blackhat.com/docs/us-17/thursday/us-17-Domas-Breaking-The-x86-Instruction-Set-wp.pdf

·       https://www.youtube.com/watch?v=vtV696SszsY

·       https://www.youtube.com/watch?v=cHh10Urud6U

·       https://www.youtube.com/watch?v=a4kmB1fOEJU

·       Update on Imagination’s PowerVR Mesa effort: https://indico.freedesktop.org/event/10/contributions/492/attachments/278/367/XDC 2025 PowerVR Lightening Talk.pdf

·       Daniel presented on the current status of mainline Linux wrt RISC-V at LinuxDay.at - slides: https://metaspora.org/riscv-mainline-linux-2025.pdf