Attendees: Daniel Maslowski, Jeff, Yu Bo, Chen Wang, Leon Nunes (new), Rafael, Thea, Darren, Axel, fuwei, Xavier Esteve (new)
Board Updates:
Mars: JH7110
Program Updates:
Debian
Bookworm has been released.
Trixie will support riscv64. (Yay!!!)
riscv64 will be added into the archive soon.
Fedora
Fedora 38 Package number 19320/23118 [83.6%]
zsbl→edk2→GRUB→Fedora
RV32 bootstrap going well, building rpms for minimal rootfs
Fedora 38 function testing:
Desktop support:
XFCE[pass]
LXDE[pass]
LXQT[pass]
GNOME[pass]
Budgie[pass]
Cinnamon[pass]
Mate[pass]
Sugar[pass]
Sway[pass]
KDE[pass]
deepin[Building]
Podman[pass]
Ceph [pass]
K8s [pass]
SUSE
Not targeting 32-bit (RV32)
Milk-V requests coming
Android (AOSP)
Kernel: Update the kernel module loader to handle R_RISCV_32_PCREL which LLVM is generating for some modules now.
Bionic: implement rvv version mem* and str* for riscv64 in bionic (which is contributed by sifive).
ART development moving forward: assembler changes continuing till part6 (Add macro instructions for loads and stores); add JNI macro assembler skeleton for riscv64; and some other bug fixing.
binary_translation & native_bridge_support still in rapid involvement, many pull-requests merged since last meeting.
oreboot
Factored out into a library, to be applied to VF2
Someone from Intel has run our code on their VF2 successfully
Firmware
GSoC coreboot project progressing, reviving support for RISC-V on QEMU
RISC-V
Shakti processor (Prasanna)
Slides: (pdf link)
Program status
VisionFive V2
49 boards shipped, one issue remains
2 boards requested shipment from inventory
“Second call” for projects posted and announced (tech-announce)
Pioneer Box
Milk-V has offered 50 boxes to RISC-V
First proposal using Partner form
Distros emailed with deadline of June 30
Currently 8 projects and 2 distros
Work remains to finalize details of box availability, shipping, etc.
10 Unmatched boards have also been offered by SiFive
Working details directly with SiFive
VisionFive V2 for Automotive
Jeff has reached out to the Automotive SIG and begun discussions about the CAN bus on VisionFive V2
A project has been received/proposed about CAN bus for VisionFive V2 from an RISC-V member. Jeff will FWUP.
What’s cool?:
https://www.chinadaily.com.cn/a/202305/27/WS647141f4a310b6054fad5587.html - Chinese Academy of Sciences high performance RISC-V chip (Xiangshan) and operating system based on openEuler (Aolai)
https://www.prnewswire.com/news-releases/tenstorrent-partners-with-lg-to-build-ai-and-risc-v-chiplets-for-smart-tvs-of-the-future-301836779.html - Tenstorrent partnering with LG on SmartTVs
https://blog-imaginationtech-com.cdn.ampproject.org/c/s/blog.imaginationtech.com/the-gpu-of-choice-for-risc-v?hs_amp=true - Imagination GPU work for RISC-V
https://www.tomshardware.com/news/risc-v-vector-unit--semidynamics - Semidynamics has released a RISC-V Vector Unit
https://techcrunch.com/2023/05/31/the-linux-foundation-europe-launches-rise-the-risc-v-software-ecosystem-project/ - RISE Foundation focuses on RISC-V Software Ecosystem
https://www.eetimes.com/axelera-demos-early-silicon-raises-50-million/ - Axelera (European startup) raises $50M USD for chips for accelerators
https://www.espressif.com/sites/default/files/documentation/ESP32-C3%20Wireless%20Adventure.pdf - New ESP32-C3 Book. 400 pages.
https://riscv-summit-china.com/submit-my-talk.html - China Summit call for papers (English)