[Devboards Program] November 5th, Devboards Program, 2026
Greg Sterling
| Our next meeting will be tomorrow. Local times can be found by logging into LFX at https://lfx.linuxfoundation.org/tools/ or going to the Tech Meetings calendar at https://riscv.github.io/riscv-tech-calendar/. |
Greg Sterling
Meeting - Nov 5, 2026
Note: The Devboards Meeting is open to members and non-members alike.
Board Updates & Information
SpacemiT Announces The V100 Server-Class RISC-V Processor - Phoronix
SpacemiT V100 testing! - r/RISCV on Reddit
Following up on its embedded K-series chips, SpacemiT unveiled the V100 processor targeted at server-class and multi-core enterprise infrastructure.
Infineon introduced AURIX™ RC1, its first microcontroller platform built on open standard RISC-V architecture, designed to scale from traditional real-time microcontrollers to 64-bit hybrid microprocessor devices for automotive zonal, body, chassis, and central compute architectures.
Oreboot, U-Boot, & Firmware
Signed FIT Image: Verified Boot on a RISC-V Board
A comprehensive analysis published on practical cryptographic verification and Flattened Image Tree (FIT) image signing inside modern U-Boot stacks for RISC-V targets.
RISC-V Software News - November 2026
Upstream tracking reports highlight accelerated commits within the OpenSBI repository focusing on machine-mode runtime services and spec compliance heading into year-end merges.
openRuyi Introduces Ruyi Firmware: An Open UEFI Firmware Solution for RISC-V Platforms
Support UEFI GOP emulation support for AMD GPUs and video output for the builtin DC
Capable of switch on/off X100/A100 clusters
Other EDK2 firmware for RISC-V boards (will be merged into ruyifirmware later):
K3: (see above)
SG2042/2044: https://github.com/revyos/firmware-sg204x
TH1520/A210: https://github.com/revyos/ruyiedk2
Operating Systems
Ubuntu 26.10 RISC-V desktop images: what to test | NeoTeo
Ubuntu 26.10 To Include Desktop Images For RISC-V - Phoronix
Canonical announced new experimental 64-bit desktop images and singled out the SpacemiT K3 Pico-ITX single-board computer for formal hardware support, requiring updated vendor firmware for direct installation.
Ubuntu now has official desktop images for RISC-V
Canonical released desktop graphical images for riscv64 architectures with Ubuntu 26.10, transitioning away from headless-only server/CLI images.
Android 17 Available on RVA23 with RISE
The RISC-V Software Ecosystem (RISE) consortium announced that the Alibaba A210 EVB and SpacemiT K3 boards serve as the official physical deployment targets for initial Android 17 RVA23 bring-up.
RHEL 10 RISC-V developer preview
Red Hat released an updated developer preview of Red Hat Enterprise Linux 10.2 for the 64-bit RISC-V architecture, expanding upstream hardware compatibility from the SiFive HiFive Premier P550 platform to include server-class and edge targets such as the SpacemiT V100, SpacemiT K3 (Pico-ITX and CoM260), and UltraRISC UR-DP1000 (Milk-V Titan).
OpenBSD 8.0 expands RISC-V support and retires the Loongson port
The release of OpenBSD 8.0 brought major updates to its native RISC-V platform port while retiring legacy Loongson support.
Linux 7.3 Adds Support For Several Newer RISC-V Extensions - Phoronix
The Linux 7.3 merge window integrated support for discovering and enumerating several newer RISC-V ISA extensions (including Smcsrind, Sscsrind, Smcntrpmf, Ssccfg, Smcdeleg, Za64rs, and Ssqosid), along with improvements to Shadow Stack control-flow integrity handling, QoS context-switch tagging, and UEFI runtime services for system shutdown and reboot.
RISC-V Has A Nice Portable Performance Optimization With Linux 7.4 - Phoronix
The upstream Linux 7.4 kernel pull request integrated notable RISC-V architectural optimizations aimed at portable execution efficiency.
Linux Finally Making It Easier To Answer The Question: "Is This RISC-V System RVA23?" - Phoronix
Pending Linux kernel patches spearheaded by Qualcomm engineer Guodong Xu introduce a single-shot mechanism via hwprobe and /proc/cpuinfo to report RVA23U64 compliance directly to user space, eliminating the tedious requirement of querying dozens of individual mandatory ISA extensions.
RISC-V Has A Nice Portable Performance Optimization With Linux 7.4 : r/RISCV
Upstream kernel work merged for Linux 7.4—originating from Tenstorrent contributions—implements runtime detection and handling for unaligned memory accesses, making performance optimizations portable across RISC-V hardware without requiring compile-time assumptions.
Development
October-23, 2026 » GCC vs LLVM compiler toolchains for RISC-V - Ashling
An architectural study evaluated code generation parity between GCC and LLVM on RV32/RV64, highlighting that while both now share robust RVA23 and RVV 1.0 backends, LLVM's TableGen architecture offers faster turnaround for vendor-defined custom instructions.
Auto Vectorizing The RISC-V Linux Kernel Shows Promising Results - Phoronix
At Linux Plumbers Conference 2026, Andy Chiu presented research showing that enabling compiler auto-vectorization using the RISC-V Vector (RVV) extension in the Linux kernel yielded measurable performance boosts, including up to 15% in LZ4 compression, 8.4% in Btrfs, and 5% in XFS.
https://felix86.com/felix86-26-11/
The felix86 x86/x86-64-to-RISC-V dynamic binary translator released version 26.11, delivering a 22% geometric-mean performance uplift across benchmarks through superblock compilation, vectorized self-validating blocks to tame self-modifying code (SMC) stutter in PC games, and emulation fixes for x87 FPU instruction pointer (FIP) handling required by SecuROM DRM.
How CHERIoT Provides Strong and Usable Isolation Without an MMU | Queue : r/RISCV
The discussion highlights an ACM Queue paper by David Chisnall detailing how the CHERIoT (Capability Hardware Enhanced RISC Instructions for IoT) architecture implements fine-grained, unforgeable hardware capabilities to enforce spatial and temporal memory safety alongside mutual isolation on embedded RISC-V devices without requiring a full Memory Management Unit (MMU) or standard MPU.
Linux 7.4 Kernel Crypto Library Enjoying Optimized AES Implementations On x86 & RISC-V - Phoronix
Upstream Linux 7.4 integrated optimized AES cryptographic routines utilizing standard RISC-V scalar cryptography (Zk) and vector cryptography extensions.
riscv: Add initial CBQRI resctrl support [LWN.net]
Kernel maintainers posted an RFC patch set adding two-stage nested DMA translation and virtual IOMMU (vIOMMU) capabilities for RISC-V using the modern /dev/iommu (iommufd) infrastructure.
Silent Degradation during Auto-Vectorization of bf16/fp16 on RISC-V Under LLVM
A compiler research paper tracked how LLVM/Clang vectorization pipelines degrade instruction quality when handling bfloat16 and float16 types, identifying strided memory access and predication overhead as key bottlenecks.
Initial Zhihe A210 support using SCMI clocks and resets
Han Gao adds inital Zhihe A210 support using SCMI (instead of RPMI, since SCMI is more comprehensive than RPMI right now).
What’s Cool
Developer Compiles RISC-V CPU Into Qwen AI Model and Runs Doom on It
AI model gets a 32-bit RISC-V CPU compiled directly into its weights, then runs DOOM on it
The implementation of Qwenputer raises some interesting concepts and solutions. For example, the developer used Qwen’s Gated DeltaNet (GND) state as RAM, which Agrawal reckons is “a pretty neat trick.” They admit that using these ‘fast weights’ as RAM isn’t an original concept, but modifying Qwen 3.5 this way does seem to be a first.
An open-source developer released RV32I-Sim, a dependency-free 32-bit RISC-V software emulator written entirely in ANSI C that features a custom ELF32 loader, memory-mapped UART, and 100% pass rates across all 42 official unprivileged rv32ui architectural compliance tests validated via GitHub Actions CI.
The release of Pharo 14 introduces native Just-In-Time (JIT) compilation support for RISC-V architectures, expanding the dynamic Smalltalk-inspired language environment to run with full hardware execution speed on RISC-V processors.
r/RISCV on Reddit: Booting xv6-riscv64 on a Raspberry Pi Pico 2 (RP2350) with Software Emulator!
An open-source developer successfully ported and booted the 64-bit Unix-like OS xv6-riscv64 on a Raspberry Pi Pico 2 microcontroller by writing a custom software emulator that fits a full RV64IMC CPU, Sv39 MMU, PLIC/CLINT, and VirtIO disk within the chip's constrained 520 KB SRAM footprint.
A developer trained a fully connected neural network (144→64→64→10) for MNIST digit classification and applied post-training int8 quantization to compress the weights from 54.5 KB down to 13.6 KB, allowing the model to fit and execute directly on a memory-constrained SiFive FE310-G002 RISC-V microcontroller with cycle-accurate hardware profiling.
The Zijf proposed extension should be ±128MiB : r/RISCV
A community proposal argues that the upcoming RISC-V "Zijf" extended-jump extension should support at least a ±128 MiB direct branch range rather than the smaller ±8 MiB/±16 MiB ranges under discussion, pointing out that JIT compilers require single-instruction atomic patching across large multi-threaded code caches.
Alibaba’s RISC-V IP powers over 6 billion shipped chips as tech giant targets AI, autos
Alibaba’s research arm, DAMO Academy, announced at the RISC-V China Summit that cumulative shipments of chips powered by its open-source XuanTie RISC-V processor IP have exceeded 6 billion units as the company pivots toward automotive electronics and edge-AI compute.
A developer successfully cross-compiled and ported Valve's Source engine to run Half-Life 2 natively on a 64-bit RISC-V Milk-V Jupiter SBC (SpacemiT K1 SoC) paired with an external AMD Radeon R9 290 GPU over a PCIe riser, hitting 57–59 FPS at 720p using DXVK-native on Vulkan.
Developer Tommy Thorn published SmolRV64, a clean-sheet, 64-bit RISC-V application processor written in Verilog that implements a 4-way superscalar out-of-order (OoO) pipeline with register renaming, non-blocking L1/L2 caches, hardware page walks, and Sv39 MMU support—successfully booting stock Ubuntu Linux, running Geekbench 5/6, and rendering native X11 Quake at over 30 FPS on a Xilinx Kintex UltraScale+ FPGA clocked at 166.67 MHz.
Miscellaneous Notes
https://mary.kevinmx.top/default/pioneer.html
Notes on addressing a Pioneer box stability issues and repasting if possible.
Computer Architectures Education
Pioneer projects.
Ubuntu support for microcontroller boards
Why AI workloads are accelerating RISC-V adoption
An industry analysis on how demand for heterogeneous compute, workload-specific co-processors, and open vector extensions is driving silicon teams toward RISC-V.
RISC-V Architecture: What Engineers Need to Know in 2026
A practitioner guide outlining the transition from basic development board prototyping to structured verification IP, safety compliance, and custom instruction sign-off.
LLMs are making formal software verification feasible at a much larger scale \ Anthropic
Anthropic partnered with Theorem to demonstrate that frontier LLMs can autonomously write formal mathematical proofs (in Rocq) verified against compiled RISC-V assembly code, proving crash-freedom and memory safety across 239 entry points in 123 open-source libraries while finding and patching edge-case bugs that escaped trillions of fuzz runs.
FADU FC5164, the SSD Controller of Sandisk DC SN861, Is a RISC-V SoC : r/RISCV
Hardware analysis of the Sandisk DC SN861 enterprise PCIe 5.0 NVMe SSD reveals it is powered by FADU's FC5161/FC5164 16-channel controller, which integrates a heterogeneous RISC-V architecture combining SiFive 64-bit S51-MC application cores and 32-bit E31-MC real-time microcontroller cores.
Community members noted that Intel has quietly exited RISC-V International, sparking debate over whether the move reflects broader cost-cutting and a refocus on core x86 silicon or if it impacts ongoing speculation around Intel foundry partnerships with RISC-V AI hardware vendors like Tenstorrent.
RISC-V compute module brings ESP32-P4 to Raspberry Pi CM4/CM5 carriers - LinuxGizmos.com
RELOC unveiled the SCINTIX P4, a compute module adopting the standard 55 × 40 mm Raspberry Pi CM4/CM5 dual board-to-board connector footprint powered by Espressif's dual-core 400 MHz RISC-V ESP32-P4 microcontroller, an ESP32-C6 wireless companion (Wi-Fi 6, BLE 5, 802.15.4), and an onboard 10/100 Ethernet PHY.
European RISC-V Industrial Computing Initiative
The non-commercial European RISC-V Industrial Computing Initiative (ERICI) launched to define and verify an open-source reference software and hardware stack for industrial PCs, combining an RVA23 SoC, HFI BIOS firmware, the gRouvr partitioning hypervisor, a real-time RTOS partition (QSOE), and a Linux operator/HMI partition running side-by-side on isolated cores.
RISC-V International
Events
RISC-V Day Tokyo 2026 Autumn (November 11)
RISC-V Association Japan announced the complete program for RISC-V Day Tokyo 2026 Autumn at the University of Tokyo, featuring hands-on morning IC design/tapeout tutorials (GF180MCU analog and digital RTL) followed by keynotes and technical sessions on 2nm edge AI accelerators, FreeBSD Linuxulator compatibility, and Tenstorrent’s Open Chiplet Atlas (OCA).
https://riscv.epcc.ed.ac.uk/community/workshops/sc26-workshop/