Fwd: RISC-V ICE-V DevBoard Program Announce

[Jeff Scheel]

It's come to my attention that perhaps the reason that we did not receive many projects is that the program was not well announced.  So, I'm working to correct that.

Please apply if you have project candidates.

-Jeff

--

Jeff Scheel (he/him/his)

Linux Foundation, RISC-V Technical Program Manager

---------- Forwarded message ---------
From: Jeff Scheel <je...@riscv.org>
Date: Thu, Feb 2, 2023 at 1:42 PM
Subject: RISC-V ICE-V DevBoard Program Announce
To: tech-announce <tech-a...@lists.riscv.org>

The RISC-V DevBoards Program would like to extend the project solicitation phase for the ICE-V board from QWERTY Embedded Design until February 28, 2023.  

This developer board can be thought of as a combination of an ESP32 SOC and a small FPGA and has the following details:

• 82 mm x 32 mm board
• ESP32C3HN4 SOC
• 400 KB SRAM
• 384 KB ROM
• Lattice iCE40 FPGA (5k LUTs)
• Wifi
• Bluetooth
• 1- USB
• GPIO for serial
• ADC
• I2C

These compact boards should be well suited for educational and prototyping activities.  If you have a project, please apply by February 28, 2023 at the form found on the RISC-V Developer Boards "Details" page at:

https://riscv.org/risc-v-developer-boards/details/

Quantities are limited and projects will be evaluated on impact and timing of submission.

Please send questions to devboa...@riscv.org.

Thanks,

-Jeff

--

Jeff Scheel (he/him/his)

Linux Foundation, RISC-V Technical Program Manager