[RISC-V][Devboards Program] September 17th, Devboards Program, 2026

[Greg Sterling]

Our next meeting will be tomorrow.  Local times can be found by logging into LFX at https://lfx.linuxfoundation.org/tools/ or going to the Tech Meetings calendar at https://tech.riscv.org/calendar/.

The agenda will focus on standard topics:

• Program updates from RISC-V
• Board and Project updates
• Future Board Program Discussion
• What's cool?
  
• Misc Notes

Any topics, updates, or information can as always either be raised at the beginning of the meeting or added to our agenda document, Dev Board Group Minutes (moved back to Google Docs).  Please note we have migrated away from the Confluence for meeting minutes.  Please reach out if you have any issues viewing the meeting minutes.

Thanks, and I look forward to seeing you tomorrow!

Greg Sterling (RISC-V International)

[Greg Sterling]

Thanks everyone for another great meeting all!

Below is the meeting minutes.

Greg Sterling (RISC-V International)

Meeting - September 17, 2026

Note: The Devboards Meeting is open to members and non-members alike.

Disclosure

Board Updates & Information

YuzukiNeko - A Linux-capable Allwinner F101 RISC-V SBC with Raspberry Pi Pico form factor - CNX Software

• YuzukiHD has made another open-source hardware Linux SBC. YuzukiNeko is a Raspberry Pi Pico-sized single board computer powered by a new Allwinner F101 RISC-V SoC.

r/RISCV on Reddit: Repasted K3 CoM260 - "temps" are higher, but fans are slower and quieter

• Replaced thermal paste and added thermal pads on memory. 

 

Oreboot, U-Boot, & Firmware

https://qsoe.net/hfi/hfi-bios-1.4.html

• HFI BIOS 1.4 with support of VisionFive 2

• r/RISCV - VisionFive 2 was user-unfriendly upon unboxing. Not anymore!

• HFI — Harmonic Firmware Initiative · QSOE Systems  

Operating Systems

Xen boots a guest on real RISC-V hardware: HiFive P550

• Big milestone for the Xen on RISC-V effort: Xen now boots a guest domain on physical RISC-V hardware, not just QEMU. Oleksii Kurochko and I, Baptiste Le Duc, got it there as Hypervisor and Kernel Engineers at Vates.

Linux Kernel CVEs to Patch by Device: 6 - 12 Sep 2026

• Upstream maintainers patched over 400 vulnerabilities across Linux kernel branches (5.10 through 6.12+), directly affecting embedded, edge, and server-class RISC-V Linux distributions.

 

Development

RISC-V for Production Embedded Systems | Better Devices Blog

• A field assessment shows RISC-V is now a fully mature option for deeply embedded microcontrollers (replacing Cortex-M0/M3), though toolchain setup for safety-critical (ISO 26262) applications still trails Arm. 

CPython Officially Adds RISC-V Support As a Tier 3 Platform - InfoQ 

What’s Cool

Infineon maps RISC-V’s role in automotive zone controllers at Hot Chips 2026 | LavX News

• Infineon presented RISC-V as a flexible ISA for automotive zone controllers, where real-time control, AI inference, connectivity, safety, and cost must share one chip. The company said toolchains, SoC design, power use, and standardized profiles will decide adoption.

Canonical Evolution of Enterprise Open Source RISC-V at Hot Chips 2026 - ServeTheHome

• Canonical presented the Evolution of Enterprise Open Source RISC-V at Hot Chips 2026. 

felix86 26.09 

• Improved performance substantially this month, across multiple integer and SIMD instructions, as well as compilation time. Below are some measurements of benchmarks running under felix86 26.08, felix86 26.09, and natively. These benchmarks are built for both x86-64 and RISC-V and have any hand-written assembly or intrinsics disabled, as the x86-64 side of benchmarks may have been more optimized.

A UPS For Your Pi That’s A Little Different | Hackaday

• A custom uninterruptible power supply design uses a low-cost CH32 RISC-V microcontroller to handle precision power regulation and telemetry communication with host SBCs. 

Some projects from RevySR:

• gnuk-f101

• Gnuk OpenPGP token firmware for Allwinner F101 (YuzukiNeko)

• canokey-riscv

• CanoKey firmware for Allwinner F101 and CanMV K230D

• openocd

• OpenOCD/CK-HAD for XuanTie chips which enables debugging via DAPLink

• So you can use cheap boards like CH347/FT2232 or just DAPLink to debug

• Currently tested on K230D/F101/TH1520

• (which would require a CKLink debugger otherwise)

AMD Expands ROCm Support To RISC V Datacenter Servers

• SiFive, AMD Demonstrate ROCm AI Workloads on RISC-V Datacenter Platform - EE Times Asia 

• This SiFive partnership lines up with that AI data center bet by trying to make ROCm the glue across different CPU architectures, not just x86.

 

Miscellaneous Notes

Your Nvidia GPU has dozens of RISC-V cores inside it, and one of them took over a huge part of the graphics driver

• Those RISC-V cores are in Nvidia's GPUs, but they're not in the shader cores. Instead, they're in the collective of small management processors doing all kinds of additional work around the graphics processing, and Nvidia reckons each GPU has 10 to 40 of them, depending on the model. 

Quintauris expands RISC-V ecosystem with new industry partnerships - New Electronics

• Quintauris has broadened its technology ecosystem through a series of new partnerships aimed at accelerating the adoption of RISC-V in industrial and automotive applications.

Events

RISC-V Summit China 2026

• 2026-10-18 through 2026-10-20