Hardware counters in the Milk-V Pioneer

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Kilian Peiro

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Sep 30, 2024, 11:54:02 AMSep 30
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Hi everyone!

We recently got a Milk-V Pioneer board and we would like to know if there is any information regarding hardware counters. So far, we are able to measure cycles, time and instructions via perf.

We were wondering if there is any document with a listing of other available hardware counters. Take for example in the SiFive Unmatched documentation, there is the "SiFive U74-MC Core Complex Manual; 21G2.01.00", which provides the listing in "Section 3.9.5 Event Selector Encodings".

Looking around, we found the "SG2042 Technical Reference Manual; May 16, 2023", but starting at "Chapter Five", all sections are marked as "TODO".

Kind regards,
Kilian

Nick Brown

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Sep 30, 2024, 12:02:23 PMSep 30
to Kilian Peiro, RISC-V Developer Board Community
Hi Kilian,

I'd be interested in this too - there are obviously a selection which are listable via perf (sounds like you found those), however I have found some strange/surprising behaviour with them where the numbers don't always make sense (I wasn't sure if this was because they are labelled incorrectly from perf or if it's an error on my side).

Cheers,
Nick


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To: RISC-V Developer Board Community <devboard-...@riscv.org>
Subject: Hardware counters in the Milk-V Pioneer
 
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Han Gao/Revy

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Oct 3, 2024, 8:41:00 AMOct 3
to RISC-V Developer Board Community, n.b...@epcc.ed.ac.uk, Kilian Peiro
Some links worth referring to
https://lore.kernel.org/all/IA1PR20MB4953DD82D0...@IA1PR20MB4953.namprd20.prod.outlook.com/
https://github.com/sophgo/linux-riscv/blob/sg2042-dev-6.6/arch/riscv/boot/dts/sophgo/mango.dtsi#L42-L131

perf event
./perf stat -a \
>    -e l1_icache_access \
>    -e l1_icache_miss \
>    -e itlb_miss \
>    -e dtlb_miss \
>    -e jtlb_miss \
>    -e inst_branch_mispredict \
>    -e inst_branch \
>    -e inst_store \
>    -e l1_dcache_read_access \
>    -e l1_dcache_read_miss \
>    -e l1_dcache_write_access \
>    -e l1_dcache_write_miss \
>    -- openssl speed rsa2048
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