how to use memory resources for IGLOO2 board?

[Jian Zhang]

As I am aware of, memory resources in IGLOO2 are 34  RAM 1K and 31  RAM 18K.  That is around  74KB ram, and 256KB eNVM.  

Are there some pure verilog way to use these memory resourses?

1. Years ago, I am using the following verilog way in altera FPGAs to use ram resources. Does it works for microsemi FPGAs?

    I will verify it tomorrow as soon as possible. 

2. eNVM are a kind of onchip rom resource, right? Are there any pure verilog way to read and write it? 

    

For question 1 or 2, if the answer is NO, I am also ok with a smartDesign way,  Please let me know what the right way is to use it!

==================================

examples that use ram in Altera FPGAs

==================================

module single_port_ram 

#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)

(

input [(DATA_WIDTH-1):0] data,

input [(ADDR_WIDTH-1):0] addr,

input we, clk,

output [(DATA_WIDTH-1):0] q

);

// Declare the RAM variable

reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];

// Variable to hold the registered read address

reg [ADDR_WIDTH-1:0] addr_reg;

always @ (posedge clk)

begin

// Write

if (we)

ram[addr] <= data;

addr_reg <= addr;

end

assign q = ram[addr_reg];

endmodule

[Antti Lukats]

On Friday, 16 November 2018 19:14:48 UTC+1, Jian Zhang wrote:

As I am aware of, memory resources in IGLOO2 are 34  RAM 1K and 31  RAM 18K.  That is around  74KB ram, and 256KB eNVM.  

Are there some pure verilog way to use these memory resourses?

yes, inference works.

 

1. Years ago, I am using the following verilog way in altera FPGAs to use ram resources. Does it works for microsemi FPGAs?

    I will verify it tomorrow as soon as possible. 

it looks like it should. Something very similar for sure does :)

 

2. eNVM are a kind of onchip rom resource, right? Are there any pure verilog way to read and write it? 

    

yes, you can access it over AHB Bus, your code can be very standard verilog, but you need to have minimal AHB bus support included.

 

For question 1 or 2, if the answer is NO, I am also ok with a smartDesign way,  Please let me know what the right way is to use it!

answers to question 1, 2 do not matter for the SmartDesign, you pretty much need some SmartDesign block anyway, but you can wrap it immediately into your toplevel verilog

https://github.com/micro-FPGA/riscv-contest-2018/wiki/FPGA-Design

Please look there, it has simple verilog top that used pre-initialized by MSS LSRAM, for access to eNVM from your code you need to expose the other AMBA bus and connect to it

[Antti Lukats]

On Friday, 16 November 2018 19:14:48 UTC+1, Jian Zhang wrote:

As I am aware of, memory resources in IGLOO2 are 34  RAM 1K and 31  RAM 18K.  That is around  74KB ram, and 256KB eNVM.  

Are there some pure verilog way to use these memory resourses?

1. Years ago, I am using the following verilog way in altera FPGAs to use ram resources. Does it works for microsemi FPGAs?

    I will verify it tomorrow as soon as possible. 

2. eNVM are a kind of onchip rom resource, right? Are there any pure verilog way to read and write it? 

    

For question 1 or 2, if the answer is NO, I am also ok with a smartDesign way,  Please let me know what the right way is to use it!

I answered too short, I guess others have same problem.

IGLOO2 is probably the HARDEST target (if considering both fast+small designs) for the contest from all FPGA's, even proasic3 (it has 128 Byte ROM usable for bootstrap) is easier!

There is no easy solution.

Fast design

=========

1) LUTROM based bootstrap to pull code from SPI flash, you need to provide your tools to program the SPI flash.. :(

if you do not have them now, it can take days to create a solution

(you need a SoC with some other SoftCPU and some C code, and and time is ticking..)

2) LUTROM based bootstrap with UART bootloader, that might be easiest way, it would avoid the need to solve the issue "how can I program the SPI flash on creative board", you can use some SREC loader or implement your own

3) you can bootstrap from AHB connected eNVM and copy the code to inferred LSRAM

4) XiP based bootstrap to copy linear SPI flash to LSRAM - this is what spinalHDL uses

Small design

==========

1) XiP from eNVM using eSRAM as data memory

you can not use LSRAM for code for the small design as each primitive burns 36 LUT's. So using eSRAM is pretty much a must, and if you use eSRAM you can equally well use eNVM

2) XiP from SPI flash using eSRAM as data memory. again you need tools to program the flash, and there is no benefit over XiP from eNVM 

===

I am reading (again) ARM_IHI0033A (AHB Lite protocol spec) and debugging a wrapper around the SmartFusion2/IGLOO2 MSS block, still half way done - simulating still in vivado, need to move to Libero/Modelsim soon.

Antti

[Eric Smith]

On Fri, Nov 16, 2018 at 1:54 PM Antti Lukats <antti....@gmail.com> wrote:

you can not use LSRAM for code for the small design as each primitive burns 36 LUT's.

Uh oh. I was planning to use LSRAM, and wasn't aware of such an issue. What do those 36 LUTs do? I wonder how many LUTs it will take to interface to AHB Lite for eSRAM/eNVM instead. My core currently uses an async-SRAM-like interface to memory.

[Jian Zhang]

    Thanks antti  very much for the rich feedback.

    I don't prefer to access spi rom out side of the chip right now. 

    So the four onchip memory types are my choices(eNVM, LSRAM, uSRAM, eSRAM).

    0) what IP from IP catlog should I use to take use of eNVM? I cannot find one

    1)After some digging in ip catlog(in Libero SOC), I found a ip named "CoreAHBLSRAM",

    Description: The CoreAHBLSRAM provides access to the embedded large SRAM blocks present on SmartFusion2 family devices through AHB-Lite slave interface. It will facilitate convenient access to            SRAM by AHB masters. Read and write transactions on the AHB are converted into corresponding transfers on the LSRAM or uSRAM.

 

     Ok, it looks this IP is able to use LSRAM and uSRAM resources with ahb. I will definitely try this first today.

    2) Another IP named CoreMemCtrl
    Description: The Memory Controller is an AHB slave component which supports access to external SRAM and Flash memory resources. The core uses 1 slave slot on the AHB bus. 

    Is it able to access the spi rom outside of the chip?   AHB compatible?  if it can, it will be good.

  

    3)RAM1K18 and RAM64x18   are also found in ip catlog. 

      It means we can instantiated that to use it. But the input/output signals are a lot as following.I need more test to know how to access the memory interface  

 

      RAM1K18 RAM1K18_0(

        // Inputs

        .A_CLK         ( A_CLK ),

        .A_DOUT_CLK    ( A_DOUT_CLK ),

        .A_ARST_N      ( A_ARST_N ),

        .A_DOUT_EN     ( A_DOUT_EN ),

        .A_BLK         ( A_BLK ),

        .A_DOUT_ARST_N ( A_DOUT_ARST_N ),

        .A_DOUT_SRST_N ( A_DOUT_SRST_N ),

        .A_DIN         ( A_DIN ),

        .A_ADDR        ( A_ADDR ),

        .A_WEN         ( A_WEN ),

        .B_CLK         ( B_CLK ),

        .B_DOUT_CLK    ( B_DOUT_CLK ),

        .B_ARST_N      ( B_ARST_N ),

        .B_DOUT_EN     ( B_DOUT_EN ),

        .B_BLK         ( B_BLK ),

        .B_DOUT_ARST_N ( B_DOUT_ARST_N ),

        .B_DOUT_SRST_N ( B_DOUT_SRST_N ),

        .B_DIN         ( B_DIN ),

        .B_ADDR        ( B_ADDR ),

        .B_WEN         ( B_WEN ),

        .A_EN          ( A_EN ),

        .A_DOUT_LAT    ( A_DOUT_LAT ),

        .A_WIDTH       ( A_WIDTH ),

        .A_WMODE       ( A_WMODE ),

        .B_EN          ( B_EN ),

        .B_DOUT_LAT    ( B_DOUT_LAT ),

        .B_WIDTH       ( B_WIDTH ),

        .B_WMODE       ( B_WMODE ),

        .SII_LOCK      ( SII_LOCK ),

        // Outputs

        .A_DOUT        ( A_DOUT_net_0 ),

        .B_DOUT        ( B_DOUT_net_0 ),

        .BUSY          ( BUSY_net_0 ) 

        );

BR,

Jack  

[Jian Zhang]

By the way, 256KB eNVM(embedded non-volatile memory) seems an excellent place to place my bootloader code.

So it would be my first priority to use it.

Then other onchip ram resources.

[Antti Lukats]

On Saturday, 17 November 2018 03:33:32 UTC+1, Jian Zhang wrote:

    Thanks antti  very much for the rich feedback.

    I don't prefer to access spi rom out side of the chip right now. 

    So the four onchip memory types are my choices(eNVM, LSRAM, uSRAM, eSRAM).

    0) what IP from IP catlog should I use to take use of eNVM? I cannot find one

There is none, it can not be instantianted as memory IP, you need to have it like this 

This is the HPMS hard block that includes eSRAM and eNVM, at top is the FIC0_USER_Master AHB bus, this is where you need to connect your IP core !

 

    1)After some digging in ip catlog(in Libero SOC), I found a ip named "CoreAHBLSRAM",

    Description: The CoreAHBLSRAM provides access to the embedded large SRAM blocks present on SmartFusion2 family devices through AHB-Lite slave interface. It will facilitate convenient access to            SRAM by AHB masters. Read and write transactions on the AHB are converted into corresponding transfers on the LSRAM or uSRAM.

 

     Ok, it looks this IP is able to use LSRAM and uSRAM resources with ahb. I will definitely try this first today.

this is just a AHB wrapper around LSRAM, you can use it same way as the eSRAM/eNVM in the HPMS

 

    2) Another IP named CoreMemCtrl
    Description: The Memory Controller is an AHB slave component which supports access to external SRAM and Flash memory resources. The core uses 1 slave slot on the AHB bus. 

    Is it able to access the spi rom outside of the chip?   AHB compatible?  if it can, it will be good.

  

This is AHB bus component to control Parallel bus SRAM and Flash devices it can not be used for SPI Flash 

It is better to add them to systembuilder canvas and export signals, but you can use the primitives too

 

[BabakR]

Hi Jian,

The eSRAM (~80KB) and eNVM (256 KB flash) is in the HPMS block of Igloo2 device. HPMS has an AHB slave interface, You can have your own AHB master in FPGA fabric to connect to HPMS AHB slave and connect to the eSRAM and eNVM via that. The eSRAM is located in offset 0x2000_0000 and eNVM is located in offset 0x6000_0000 in the HPMS AHB bus matrix.

uSRAM and LSRAM are fabric memory blocks. You can infer those RAMs (if you don't want to instantiate them from the tool) in pure Verilog similar to the example you provided below. I am not sure what Synplicity defualt implementation is but you can override the default behavior by applying the syn_ramstyle attribute to control how the memory gets mapped. To map to

• RAM1K18 set syn_ramstyle = "lsram"

• RAM64X18 set syn_ramstyle = "uram"

• Registers set syn_ramstyle = "registers. 

After synthesis check the netlist or synthesis log files to make sure that Synplicity has done the inference correctly. 

Hope this helps. 

[Tommy Thorn]

Hi Jian,

for the embedded memory blocks, you might find https://www.microsemi.com/document-portal/doc_download/129966-inferring-microsemi-smartfusion2-ram-blocks-app-note

relevant; it details how to infer them from more or less generic Verilog/VHDL templates.

Also, anyone using the Microsemi parts should be familiar with https://www.microsemi.com/document-portal/doc_download/132008-ug0445-smartfusion2-soc-fpga-and-igloo2-fpga-fabric-user-guide

Besides the non-ability to initialize memory, not being able to initialize registers to known values combined with the non-zero overhead of added reset to flops, makes this FPGA a bit harder to use.

Tommy

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[Antti Lukats]

On Saturday, 17 November 2018 20:30:42 UTC+1, BabakR wrote:

Hi Jian,

The eSRAM (~80KB) and eNVM (256 KB flash) is in the HPMS block of Igloo2 device. HPMS has an AHB slave interface, You can have your own AHB master in FPGA fabric to connect to HPMS AHB slave and connect to the eSRAM and eNVM via that. 

80KB? Product table say 64K

Antti

[Antti Lukats]

On Saturday, 17 November 2018 20:31:03 UTC+1, tommy wrote:

Hi Jian,

for the embedded memory blocks, you might find https://www.microsemi.com/document-portal/doc_download/129966-inferring-microsemi-smartfusion2-ram-blocks-app-note

relevant; it details how to infer them from more or less generic Verilog/VHDL templates.

Also, anyone using the Microsemi parts should be familiar with https://www.microsemi.com/document-portal/doc_download/132008-ug0445-smartfusion2-soc-fpga-and-igloo2-fpga-fabric-user-guide

Besides the non-ability to initialize memory, not being able to initialize registers to known values combined with the non-zero overhead of added reset to flops, makes this FPGA a bit harder to use.

Tommy

all register and RAM init should be considered a RANDOM, they really are..

g

Antti 

[BabakR]

I was quoting SmartFusion2 product table. It says without SECDED (ECC) it can be up to 80 KB.

[Antti Lukats]

On Saturday, 17 November 2018 20:30:42 UTC+1, BabakR wrote:

Hi Jian,

The eSRAM (~80KB) and eNVM (256 KB flash) is in the HPMS block of Igloo2 device. HPMS has an AHB slave interface, You can have your own AHB master in FPGA fabric to connect to HPMS AHB slave and connect to the eSRAM and eNVM via that. The eSRAM is located in offset 0x2000_0000 and eNVM is located in offset 0x6000_0000 in the HPMS AHB bus matrix.

INDEED there is 80KByte and not 64KByte eSRAM, the 5 th byte of ECC is accessible in SECDED disable mode, I did not think of that

well, I guess there is not so much need for anyone to go hunting those extra 16KByte of eSRAM

g

Antti