Creative board official documentation, in github

[Antti Lukats]

Hi,

not sure if all have this info already, I figured it out only about an hour ago after doing registration at Future website, they sent immediately this

https://github.com/Future-Electronics-Design-Center/Creative-Eval-Board

So whatever there is, is the official place for documentation and demos.

Ah, be aware that the UART RX and TX are used sometimes RX, is RX something RX is TX, the usual thing :)

G3 is output from FPGA, H3 is input, no matter how they are named..

g

Antti

[Tommy Thorn]

Thanks Antti,

that's useful albeit at this point I'm not sure...

IIUC, it seems to be the conclusion that all the required workloads can run from

internal memory?  That changes everything as you no longer have to interface

with their external DRAM controller, at which point you don't really need to care

about the Libero system builder.  Also, not having to implement caches simplifies

the core significantly.

I still would have preferred that would have provided the exact binaries to run

to level the playing field.  Allowing custom libc implementations makes this the

wild west and further diminishes the practical value of the cores.

Tommy

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[Antti Lukats]

On Saturday, 17 November 2018 21:03:21 UTC+1, tommy wrote:

Thanks Antti,

that's useful albeit at this point I'm not sure...

;) yeah, the repo seems to be 18 days old/new.. pretty much late so or so

Ah another useless info: Microsemi provides SPI Flash bootloaders and spi flash over uart programming stuff, I found that too, well yes only for SmartFusion2, and it looked really complicated, I'd say doing it from scratch may be faster than using that bootloader concept.

 

IIUC, it seems to be the conclusion that all the required workloads can run from

internal memory?  

well this has been know pretty much from the beginning, ROM needs >16K (18?) about minimal RAM not sure, 8K is OK, probably 4K too, I had some trouble with zephyr trying to decrease the RAM requirements, but I am not sure that I did it right, so I cant say if 4K RAM is OK or not  8K is

 

That changes everything as you no longer have to interface

with their external DRAM controller, at which point you don't really need to care

about the Libero system builder.  

you pretty much need the system builder to configure the HPMS

DRAM would only come to play for small design if price of eSRAM would be sky high, it still may be set sky hi, no one knows it.

 

Also, not having to implement caches simplifies

the core significantly.

 

I guess cache use is design choice, If you can run from cache faster then single cycle tightly coupled RAM, but I am failing to see how small caches on Microsemi can be faster than fabric TCM, there may be case that EBR based cache runs at faster clock than 32 bit wide SPRAM (2 blocks) not sure about that.

 

I still would have preferred that would have provided the exact binaries to run

to level the playing field.  Allowing custom libc implementations makes this the

wild west and further diminishes the practical value of the cores.

Tommy

Right there is syscalls.c in riscv repo that includes ctrcmp, but not all are using that file, some use from libc, some write their own so it will be total random who uses what lib..

g

Antti 

[Eric Smith]

Well, I guess I'm just dumb. I have a raw binary file ucode.bin that I want to program to the eNVM, and I can't figure out how to do it.

[Antti Lukats]

On Saturday, 17 November 2018 22:08:57 UTC+1, Eric Smith wrote:

Well, I guess I'm just dumb. I have a raw binary file ucode.bin that I want to program to the eNVM, and I can't figure out how to do it.

just click and select, you may need to convert to hex before. 

but this is how it is done

Antti