Dear P4 Community:
Since its introduction a decade ago, P4 has led to a Cambrian explosion of ideas including new protocols, new applications like in-band telemetry, and new testing, validation, and formal verification techniques. P4 has become the industry standard for programming and specifying forwarding behavior. As a measure of success, one in four papers published at ACM SIGCOMM ’22 — the top conference for networking research — are built on P4 in some way.
As you may know, Intel recently announced that it will stop development of the next-generation Intel® Tofino® Intelligent Fabric Processor (IFP) products currently on its roadmap. However, we will continue to sell and support our existing Tofino® products. Intel Tofino® IFPs proved to the world that you can build fully programmable switches without compromising on performance. Tofino’s program independent switch architecture (PISA) will have a lasting effect on how packet-processing pipelines are built; it has already influenced programmable products at the edge such as SmartNICs and IPUs.
Although Tofino’s roadmap is curtailed, I’d like to make clear that the team here at Intel remains committed to P4 as the language of choice across a wide range of Intel products and platforms, including our IPUs (ASIC and FPGA). The mission of Intel Network and Edge (NEX) group remains unchanged: we design and sell products to enable network owners to decide how packets are processed and to deploy their own creative new solutions. P4 is an essential part of our roadmap for IPUs, FPGAs, DPDK, IDPK, and more.
Intel remains committed to open source and we continue to contribute to, and support, the P4 community, including the design of the P4 language, standard architectures, control APIs, and applications. And we will continue to develop open-source targets like P4TC, which integrates P4 into the Linux kernel, bringing a new level of programmability to the network edge.
Together, as a community, we can feel proud for successfully fostering a “revolution” in how industry and researchers think about networks. In the past, behaviors were baked into fixed function hardware; today, we can specify and program behaviors in software that are compiled and deployed in-situ, allowing beautiful new ideas to be tested and deployed more quickly. There is no going back.
P4 got its start when a small group got together to think about new abstractions for programmable networking. We’ve now grown into a vibrant community of researchers and practitioners who are pushing the boundaries of what’s possible across the full range of programmable targets. I’m honored to be a part of this community and I’m inspired by what we’ve accomplished and excited about what we will achieve in the future.
Sincerely,
Nick McKeown
Senior VP & GM, Senior Fellow
Network and Edge Group (NEX)
A Cavium/Marvell Octeon using vpp/dpdk for software is worth investigating. I can provide the p4tovpp/dpdk compiler, especially to a university, at a modest price. Octeon supports same data rates as FPGA. Further vpp is the most comprehensive networking data plane. Additionally, a FPGA p4c tends to restrict P4, which a software data plane P4 and vpp/dpdk won’t restrict.
Hemant
Also, with more disaggregation of networking nodes, e.g., 5G cellular, the nodes need 400-800G rate, crypto, state machine, and timers at large scale. Can’t get all these features in P4 except with MNK’s P4toVPP/DPDK compiler.
Hemant
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I thank Nick and the Barefoot team for developing Tofino and P4 compiler for it – great product.
However, product development is tricky. I develop a switch product using Tofino II. I take the switch to a cloud provider who likes it. The operator asks what roadmap for your switch is because my services will double bandwidth in four years. My reply is “no roadmap” and the operator refuses to buy my switch. I have to look at alternatives immediately.
Best,
Hemant
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