open-source rtl for nic accelerator, 400G, risc
hem...@mnkcg.com
For nic there is p4c-pna. Well, I like open source nic hardware below. Use 72-risc-v cores to get 1 Tbps nic.
li...@baldi.info
Hi Hemant,
In the documentation about PsPIN I couldn’t find any information about p4c-pna.
Does it support the new functionalities we have introduced into PNA (such as add_on_miss and rmw table entries)?
Thanks,
---
Mario
--
You received this message because you are subscribed to the Google Groups "p4-arch" group.
To unsubscribe from this group and stop receiving emails from it, send an email to p4-arch+u...@lists.p4.org.
To view this discussion on the web visit https://groups.google.com/a/lists.p4.org/d/msgid/p4-arch/21aa01da3d8f%24c578b1d0%24506a1570%24%40mnkcg.com.
hem...@mnkcg.com
They don’t discuss p4c because it’s a hardware design in Verilog. One can use P4 to program the hardware which is not discussed.
hem...@mnkcg.com
Most DPU vendors use a RMT pipeline in hardware and program the pipeline using P4. But this open hardware design and Marvell DPU use multiple RISC and ARM cores respectively. My company’s p4tovpp/dpdk compiler supports pna.p4 and knows how to run p4 on multiple cores.
--
You received this message because you are subscribed to the Google Groups "p4-dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to p4-dev+un...@lists.p4.org.
To view this discussion on the web visit https://groups.google.com/a/lists.p4.org/d/msgid/p4-dev/00c301da3e3a%248021b950%2480652bf0%24%40mnkcg.com.
li...@baldi.info
Does your p4tovpp/dpdk compiler support the new functionalities we have introduced into PNA (such as add_on_miss and rmw table entries)?
Thanks,
---
Mario
hem...@mnkcg.com
Sorry, I don’t discuss individual functionality without NDA.
To view this discussion on the web visit https://groups.google.com/a/lists.p4.org/d/msgid/p4-dev/0ad801da3e52%24b47fdd90%241d7f98b0%24%40baldi.info.