Query regarding P4 program header field to PHV field mapping

[Debobroto Das]

Hello everyone, 

Assume the following header definition: 

header MyHeader {
bit<7>  field_1;

bit<10>  field_2;
}

Now consider P4 supported switch with a packet header vector that contains 10 fields.  Among them, two are 16 bits wide and the rest of them are 8 bit wide.  Now to map the fields of MyHeader  we can either map field_2 to a 16 bit wide PHV field or merge two 8 bit wide PHV field together.  I guess the task is handled by a compiler backend. 

My question is,  how a compiler backend decides which field of P4 program to be  mapped to which fields in the PHV? I guess it should be a version of Knapsack optimization problem?

Secondly, if a 10 bit header field is mapped to two 8 bit wide field in the PHV, then there should be some kind of padding to be included. Does the parser handles the task of including the padding or it is does afterwards? 

[Nate Foster]

PHVs are a concept used by specific targets, but do not appear in the P4 Language Specification. So you may need to direct your question to the vendor of the hardware that you are using.

Similarly, questions about how a P4 compiler for a particular target maps the source program to the various gadgets supported in hardware is a question for vendors. There is an NSDI '15 paper on the topic (https://www.usenix.org/conference/nsdi15/technical-sessions/presentation/jose). 

Finally, the P4 Language Specification says:

Targets may impose additional constraints on header types—e.g., restricting headers to sizes that are an integer number of bytes.

If the target does not impose this constraint, then any padding used internally would be an internal implementation detail. In particular, it should not be visible to programmers in the sense that operations like packet_in.extract or packet_out.emit would need to handle headers that are not an integer number of bytes without any visible padding.

Hope that helps.

-N

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