Agenda for our November meeting, this coming Monday, November 20th. See you there!

[Ray Simar]

Hi all,

I am looking forward to our November meeting this Monday, November 20th.

First, here’s our Zoom link for our meeting (8 AM US Pacific time): https://riceuniversity.zoom.us/j/94249046147?pwd=YzBHTzdHWWVFY09YNHdvTjREME84Zz09 

We had some great discussion via email about getting the benchmarks pulled together.  We have been making some more progress.  Many thanks to Jennifer for an update and David Harris for pushing through the benchmarks using Wally.  

Here’s Jennifer’s latest update…

Thanks for all the feedback and conversation, all!  Here is a summary of what I have generated…

 

Data: https://drive.proton.me/urls/503GADCXJM#OtYw1dINdlpP

 

Cores/Architectures:

• OpenHW CV32E40P v1.3.2
• RV32I
• RV32IM
• RV32IMC
• RV32IMFC
• OpenHW CV32E40X commit b658fbe0
• RV32I
• RV32IM
• RV32IMC
• RV32IMC_Zba_Zbb_Zbc

 

Toolchain: Embecosm RISC-V GCC 13.1.0

 

Optimization levels: “-msave-restore -Oz”, “-Oz”, “-msave-restore -Os”, “-Os”, “-msave-restore -O2”, “-O2”, “-O3”, “-Ofast”

 

Metrics:

• From build:
• object size
• app size
• # instructions
• # 32b
• # 16b
• From simulation:
• # cycles
• # retired
• # fetches
• # loads
• # stores

 

Best,

Jennifer

If you explore Jennifer’s proton drive link above, she has created a number of graphs.

David H. got a lot of the runs working but hit a snafu on the floating-point cubic benchmark.  As a result, I think he has the non-floating-point runs working.

As Dave P has suggested, let use this Monday’s meeting to get an overview of the data we’ve collected and the relationships between the different efforts.  We can see what are the gaps and overlaps we might have.

From our earlier discussion, here is the list of the experiments Dave would like to see:

1. ARM Performance gain over 7 GCC generations [DONE, in paper]
2. Code size different ARM vs RISC-V [Embench done, need for CoreMark & Dhrystone] - based on GCC
3. Performance change if optimize for code size for ARM and RISC-V - based on GCC
4. Code size change if optimize for performance for ARM and RISC-V - based on GCC
5. Performance/Code size  change if use CLANG for ARM and RISC-V
6. Performance/Code size  change if use LLVM for ARM and RISC-V
7. Performance/Code size  change if add M extension to RV32I - based on GCC
   
8. Performance/Code size  change if add C extension to RV32IM - based on GCC
   
9. Performance/Code size  change if add BitManip extension to RV32IMC - based on GCC
   
10. Performance/Code size  change if add F extension to RV32IMCB (should be zero) - based on GCC
    
11. Performance/Code size  change if add D extension to RV32IMCBF (should be zero) - based on GCC

You can find Dave’s current draft of the paper here: https://drive.google.com/file/d/1dUjVoaAUuMFqDzfItZTk1xu7aEsDGtnV/view

Does anyone have any other things they might like to have on the agenda?  Let me know.

See you all tomorrow!

All the best,

Ray

[David PATTERSON]

We just need to be sure we have all the results for Dhrystone and Coremark as well as Embench to make the case that Embench is much more accurate. 

I have put together this spreadsheet. If people in the know can fill in colors to show what we have (green shade), what we almost have (yellow shade), what we can't get (red shade), and grey (not applicable)---ideally before the meeting---then it might shorten the discussion.

I started based on what I know

Best,
Dave

 Checklilst

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[Ray Simar]

Hi Dave,

This is a great spreadsheet!  Let me encourage everyone to take a moment and provide an update using Dave’s color scheme.

I am also adding a bit of notation so we can see who is doing what.  Here’s the spreadsheet: https://docs.google.com/spreadsheets/d/1INHyTyf80Wb8cBRaozLwkASKFx_-T4G4tWJzthLS3iI/edit?usp=drive_web

Talk to you in an hour: https://riceuniversity.zoom.us/j/94249046147?pwd=YzBHTzdHWWVFY09YNHdvTjREME84Zz09

All the best,

Ray