Agenda for our September meeting, this coming Monday, September 18th. Welcome back!

[Ray Simar]

Hi all,

Welcome back to those who have been out on vacation and traveling!  It’s been July since we last met, so this meeting will be a great chance to do a bit of a resynch.

I took last month as an opportunity to meet with Jennifer Hellar of Cirrus Semiconductor to learn more about her work on code size and performance analysis of embedded microcontrollers.  Jennifer is a former student of mine.  She got the OK from her supervisors to share her work with.  Last month, Jennifer gave Dave and I a short overview of her work.  

We thought it would be great for the team to hear about what she and the team at Cirrus are up to.  So we have asked her to present to us this Monday.

The other thing we’d like to do is synch up on where we are with the experiments Dave has requested for the paper he is pulling together.  From an earlier discussion, here’s the list of the experiments Dave would like to see:

1. ARM Performance gain over 7 GCC generations [DONE, in paper]
2. Code size different ARM vs RISC-V [Embench done, need for CoreMark & Dhrystone] - based on GCC
3. Performance change if optimize for code size for ARM and RISC-V - based on GCC
4. Code size change if optimize for performance for ARM and RISC-V - based on GCC
5. Performance/Code size  change if use CLANG for ARM and RISC-V
6. Performance/Code size  change if use LLVM for ARM and RISC-V
7. Performance/Code size  change if add M extension to RV32I - based on GCC
   
8. Performance/Code size  change if add C extension to RV32IM - based on GCC
   
9. Performance/Code size  change if add BitManip extension to RV32IMC - based on GCC
   
10. Performance/Code size  change if add F extension to RV32IMCB (should be zero) - based on GCC
    
11. Performance/Code size  change if add D extension to RV32IMCBF (should be zero) - based on GCC

Here’s my current agenda:

• Jennifer Hellar gives us an overview of her analysis flow for code size and performance benchmarking.
• Discuss our current status on the above list of experiments.
• Work up a plan for how we can best close on the above experiments so Dave can make progress on the next draft of the paper.
• Resynch on any other issues

You can find Dave’s current draft of the paper here: https://drive.google.com/file/d/1dUjVoaAUuMFqDzfItZTk1xu7aEsDGtnV/view

Does anyone have any other things they might like to have on the agenda?  Let me know.

Here’s the Zoom link for our meeting (8 AM US Pacific time)

See you all tomorrow!

All the best,

Ray

[Ray Simar]

Here you all go: https://riceuniversity.zoom.us/j/96141628421?pwd=MTY2eHY2RVBtZG1uclo0OG9rLy9HZz09

[Jennifer Hellar]

Hi all,

 

I’ve extrapolated a bit from the list of experiments in Ray’s email below to define the parameters like toolchain version, RTL platform, etc. more fully in the attached spreadsheet Experiments.xlsx.

 

I need help from you all to

1. Fill in the missing parameters to fully define the setup.
2. Confirm that the parameters I already filled in are correct or sufficient.

 

I also attached the log of commands run to build crc32 (embench_crc32.log) in my setup.  And here are the cycle count and code size outputs (using Embecosm GCC 13.1.0) for you to compare and see if you can replicate them for the sake of consistency.

• CYCLES: 27703
• text       data        bss      total filename
• 126         15          0        141 test_main.o
• 288          0         16        304 beebsc.o
• 166       1024          0       1190 crc_32.o

 

Let me know what you think; happy to discuss in the Matrix chat or hop on a call sometime next week if that is easier.

 

Best,

 

Jennifer Hellar

Design Verification Engineer

Cirrus Logic | Jennife...@cirrus.com | +1 512.851.4095

 

 

From: Ray Simar <ray....@rice.edu>
Date: Monday, September 18, 2023 at 10:15 AM
To: emb...@lists.librecores.org <emb...@lists.librecores.org>
Cc: David Patterson <davidpa...@google.com>, jeremy....@embecosm.com <jeremy....@embecosm.com>, Jennifer Hellar <Jennife...@cirrus.com>
Subject: Re: Agenda for our September meeting, this coming Monday, September 18th. Welcome back!

Here you all go: https: //riceuniversity. zoom. us/j/96141628421?pwd=MTY2eHY2RVBtZG1uclo0OG9rLy9HZz09 On Sep 17, 2023, at 12: 04 PM, Ray Simar <ray. simar@ rice. edu> wrote: Hi all, Welcome back to those who have been out on vacation and traveling!

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[Ray Simar]

Hi Jennifer,

Thanks so much for pulling this together and point out where you need help.

I’d love to hear from the team who can help with these gaps.

Like Jennifer, I am happy to use Matrix.  I’d love to see how this tool works. :-)

All the best,

Ray

On Sep 28, 2023, at 7:58 PM, Jennifer Hellar <Jennife...@cirrus.com> wrote:

Hi all,

 

I’ve extrapolated a bit from the list of experiments in Ray’s email below to define the parameters like toolchain version, RTL platform, etc. more fully in the attached spreadsheet Experiments.xlsx.

 

I need help from you all to

1. Fill in the missing parameters to fully define the setup.
2. Confirm that the parameters I already filled in are correct or sufficient.

 

I also attached the log of commands run to build crc32 (embench_crc32.log) in my setup.  And here are the cycle count and code size outputs (using Embecosm GCC 13.1.0) for you to compare and see if you can replicate them for the sake of consistency.

• CYCLES: 27703
• text       data        bss      total filename
• 126         15          0        141 test_main.o
• 288          0         16        304 beebsc.o
• 166       1024          0       1190 crc_32.o

 

Let me know what you think; happy to discuss in the Matrix chat or hop on a call sometime next week if that is easier.

 

Best,

 

Jennifer Hellar

Design Verification Engineer

Cirrus Logic | Jennife...@cirrus.com | +1 512.851.4095

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<Experiments.xlsx><embench_crc32.log>