Agenda for our October meeting, this coming Monday, October 16th. See you there! We have a new Zoom link!

[Ray Simar]

Hi all,

I am looking forward to our October meeting this Monday, October 16th.

First, here’s a new Zoom link for our meeting (8 AM US Pacific time): https://riceuniversity.zoom.us/j/94249046147?pwd=YzBHTzdHWWVFY09YNHdvTjREME84Zz09 

I have set up this Zoom link to let us share without requiring a host to grant permission for sharing.  This was a snafu in our previous meeting.  I am working with Rice IT to see if we I can also set up others to be hosts.  Now, you should be able to log in and begin sharing without any host.  We’ll give this a test run and see if it works for us!  Back to our regular business...

Last month, Jennifer Hellar gave us an overview of the flow she has been developing to assist with Cirrus Logic’s benchmarking effort.

To help us improve our communication (remember we are a world-wide organization!) Paolo set up a Matrix room for us to chat about our Embench efforts.  If you haven’t given Matrix a try, go to https://matrix.to/#/%23embench:fossi-foundation.org  Set up an account and you can see the discussion, especially between Paolo and Jennifer.

FYI, I was a newbie to Matrix and Paolo was a big help in getting me setup.  Matrix is much like Slack.  I am using Element as my Matrix client.  If you run into any questions, give me a shout.

For this Monday, we’ll get Paolo and Jennifer to give us an update on their progress with running the experiments Dave has requested.

From an earlier discussion, here is the list of the experiments Dave would like to see:

1. ARM Performance gain over 7 GCC generations [DONE, in paper]
2. Code size different ARM vs RISC-V [Embench done, need for CoreMark & Dhrystone] - based on GCC
3. Performance change if optimize for code size for ARM and RISC-V - based on GCC
4. Code size change if optimize for performance for ARM and RISC-V - based on GCC
5. Performance/Code size  change if use CLANG for ARM and RISC-V
6. Performance/Code size  change if use LLVM for ARM and RISC-V
7. Performance/Code size  change if add M extension to RV32I - based on GCC
   
8. Performance/Code size  change if add C extension to RV32IM - based on GCC
   
9. Performance/Code size  change if add BitManip extension to RV32IMC - based on GCC
   
10. Performance/Code size  change if add F extension to RV32IMCB (should be zero) - based on GCC
    
11. Performance/Code size  change if add D extension to RV32IMCBF (should be zero) - based on GCC

Here’s my current agenda:

• Jennifer and Paolo give us an update on the status of their work.
• Discuss our current status on the above list of experiments.
• Work up a plan for how we can best close on the above experiments so Dave can make progress on the next draft of the paper.
• Resynch on any other issues

You can find Dave’s current draft of the paper here: https://drive.google.com/file/d/1dUjVoaAUuMFqDzfItZTk1xu7aEsDGtnV/view

Does anyone have any other things they might like to have on the agenda?  Let me know.

See you all tomorrow!

All the best,

Ray

[Ray Simar]

Hi all,

Just a reminder that we are using a new Zoom link for today’s meeting!  Here it is:

See you shortly!

All the best,

Ray