TASER Workshop in Prague + RISC-V PQC Crypto TG
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Markku-Juhani O. Saarinen
May 31, 2023, 6:25:06 AM5/31/23
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Hello PQC Forum!
On behalf of the TASER organizing committee:
The 3rd TASER Workshop (Topics in hArdware SEcurity and RISC-V) will be organized as a part of CHES 2023 in Prague on September 10. It will be held in-person as a half-day CHES forum, TASER, and will include a mixture of invited and submitted presentations.
For more information: https://ches.iacr.org/2023/forum.php
The workshop covers all aspects of RISC-V Hardware Security, but the specific topic for TASER 2023 is:
*Scalar and vector instruction set extensions for PQC*
As specified in the call, a full-paper submission is not necessary; 1-page PDF proposal is sufficient by the deadline of June 23, 2023 at: https://easychair.org/conferences/?conf=taser2023
--
On a closely related note (but on behalf of the Cryptographic Extensions Task Group), RISC-V International is starting a standardization effort for possible scalar and vector ISA extensions to support Post-Quantum Cryptography.
We will be kicking this effort off next Monday (June 5) at RISC-V Summit Europe TWG meetings in Barcelona, Spain: https://riscv-europe.org/twg-meetings.html
I should note the difference in scope: RISC-V International specifies the official ISA extensions that will be in RISC-V specifications (in contrast with custom instructions and CPUs, which anyone can build). Standard extensions will have mainline support in compiler toolchains (LLVM and GCC) and typically in popular pre-packaged middleware, too (OpenSSL and Linux distributions.) This has already happened with earlier RISC-V cryptography extensions.
Due to IP issues, a RISC-V signatory member must contribute instructions to be considered for inclusion into the RISC-V specifications. There are individual and academic membership options. Unfortunately (but to protect everyone that uses the ISA), RISC-V can't just lift proposed instructions from academic papers (or talks at, say, TASER) into the standards, regardless of how great they are. Such technology must be officially contributed to RISC-V by the authors/designers/owners, under an appropriate license.
Cheers,
On behalf of the TASER organizing committee:
The 3rd TASER Workshop (Topics in hArdware SEcurity and RISC-V) will be organized as a part of CHES 2023 in Prague on September 10. It will be held in-person as a half-day CHES forum, TASER, and will include a mixture of invited and submitted presentations.
For more information: https://ches.iacr.org/2023/forum.php
The workshop covers all aspects of RISC-V Hardware Security, but the specific topic for TASER 2023 is:
*Scalar and vector instruction set extensions for PQC*
As specified in the call, a full-paper submission is not necessary; 1-page PDF proposal is sufficient by the deadline of June 23, 2023 at: https://easychair.org/conferences/?conf=taser2023
--
On a closely related note (but on behalf of the Cryptographic Extensions Task Group), RISC-V International is starting a standardization effort for possible scalar and vector ISA extensions to support Post-Quantum Cryptography.
We will be kicking this effort off next Monday (June 5) at RISC-V Summit Europe TWG meetings in Barcelona, Spain: https://riscv-europe.org/twg-meetings.html
I should note the difference in scope: RISC-V International specifies the official ISA extensions that will be in RISC-V specifications (in contrast with custom instructions and CPUs, which anyone can build). Standard extensions will have mainline support in compiler toolchains (LLVM and GCC) and typically in popular pre-packaged middleware, too (OpenSSL and Linux distributions.) This has already happened with earlier RISC-V cryptography extensions.
Due to IP issues, a RISC-V signatory member must contribute instructions to be considered for inclusion into the RISC-V specifications. There are individual and academic membership options. Unfortunately (but to protect everyone that uses the ISA), RISC-V can't just lift proposed instructions from academic papers (or talks at, say, TASER) into the standards, regardless of how great they are. Such technology must be officially contributed to RISC-V by the authors/designers/owners, under an appropriate license.
Cheers,
- Markku
Dr. Markku-Juhani O. Saarinen <mj...@iki.fi>
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