Hardware Benchmarking Framework for Lightweight Cryptography
Jens-Peter E Kaps
Hello,
It is our pleasure to announce the publication of the following resources related to hardware benchmarking of submissions to the NIST Lightweight Cryptography (LWC) standardization process:
1. "A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography"
2. "Hardware API for Lightweight Cryptography"
3. "Implementer's Guide to Hardware Implementations Compliant with the Hardware API for Lightweight Cryptography," ver. 1.0
4. "Development Package for Hardware Implementations Compliant with the Hardware API for Lightweight Cryptography," ver. 1.0.
All of these resources are available at
https://cryptography.gmu.edu/athena/index.php?id=LWC
The first three of them are documents. The fourth is a development package composed of VHDL, C, and Python source files, as well as related scripts and configuration files.
Documents 2.-4. are modifications and extensions of similar resources used during the CAESAR competition, in the period 2016-2018. The differences are clearly summarized in the documents themselves.
They are aimed primarily at
- supporting optional hash functionality
- simplifying implementations and making them more uniform
- supporting alternative implementations resistant against side-channel attacks.
We propose the adoption of a uniform hardware API for any future implementations of LWC candidates targeting FPGAs, All Programmable Systems on Chip, and ASICs. We strongly encourage all submitters and supporting hardware designers to use these resources in order to assure:
A) fair comparison
B) compatibility among cores of the same algorithm developed by multiple groups
C) full third-party verification, and
D) speed-up of the development process (at least for groups starting from scratch or using the CAESAR Hardware API before).
We greatly appreciate all comments regarding a draft version of the LWC Hardware API, announced on July 16, 2019. We did our best to incorporate all the suggestions we considered consistent with our vision and goals. We hope that the current version of the API is acceptable to all submission teams, NIST, and the vast majority of designers supporting the hardware evaluation efforts.
We would like to kindly ask NIST for the endorsement of the proposed hardware benchmarking framework.
We also suggest that NIST should enforce the submission of the hardware description language code, compliant with the proposed Hardware API, for all candidates qualified to Round 2.
The deadline for such submissions could be set in the middle of Round 2, e.g., to
January 31, 2020,
to allow sufficient time for optimized implementations.
In the following 3.5 months, until January 31, 2019, our team would be happy to
- support any Round 2 submission teams with their hardware implementation efforts, by providing technical support regarding the aforementioned Development Package and its documentation
- take responsibility for the uniform implementation of several Round 2 candidates with no hardware implementations announced to date
- review any comments received from the cryptographic community, and, if justified, release the revised and extended versions of the Development Package and the related documents.
Then, in February 2020, our team would be happy to perform the comprehensive benchmarking of all submitted implementations, using selected FPGAs from two major vendors, and post the obtained results in the
- online database of results ( similar to that used during the CAESAR competition, available at https://cryptography.gmu.edu/athenadb/fpga_auth_cipher/rankings_view )
- related ePrint reports and conference publications.
Any comments regarding this proposed benchmarking effort and its timeline are very welcome!
Thanks a lot in advance for your valuable suggestions!
Jens, Kris, William, Michael, Farnoud, and Ice
Jens-Peter Kaps and Kris Gaj
George Mason University
Cryptographic Engineering Research Group
https://cryptography.gmu.edu
William Diehl
Virginia Tech
Signatures Analysis Lab
https://rijndael.ece.vt.edu/wdiehl/
Michael Tempelmeier
Technische Universität München
Lehrstuhl für Sicherheit in der Informationstechnik
https://www.sec.ei.tum.de/en/staff/michael-tempelmeier/
Farnoud Farahmand
George Mason University
Cryptographic Engineering Research Group
Ekawat Homsirikamol (a.k.a. Ice)
Independent Researcher
