We are moving towards some unit tests to validate the plot output.
Such a test already exists for schematic plot output as a kicad-cli
test and will be expanded to PCB eventually.
But, even the recent changes such as
d5bd1f5aea042a238345171b99a195da9e0eab9e were entirely intentional and
not an accidental change.
Even the original change that the d5bd1f5 commit is fixing wasn't
entirely accidental either.
But we had a discussion to switch back to the original behavior for
the exact "it's dangerous reason" of opening 6.0 designs.
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Mark