Necessary actions to make the preset events working with Intel Tigerlake

[Melis Kapotoğlu]

Hello,

I have thoroughly reviewed all discussions in this forum regarding new CPUs that lack support for preset events. I currently have a Tigerlake CPU and can operate with native events. However, I am interested in understanding the steps required to update the PAPI codebase to enable support for preset events on Tigerlake as well. In one conversation, it was mentioned that this might be a straightforward one-line change if a new processor is similar to the last generation. If I'm not mistaken, Tigerlake is very similar to ICL (Icelake). Could you provide guidance on utilizing the existing configuration added for Icelake to also support Tigerlake? 

It's worth noting that I've already updated the libpfm4 library in the PAPI codebase to accommodate Tigerlake, and I believe this should work with the necessary updates in other parts of the code.

Regards,

Melis 

[Giuseppe Congiu]

Hi Melis,

If you look at the papi_events.csv file in the papi/src/ directory, you can find the Icelake preset events:

CPU,icx

PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED:THREAD_P

PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P

PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES

# Loads and stores

PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_LOADS

PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_STORES

PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_INST_RETIRED:ALL_LOADS,MEM_INST_RETIRED:ALL_STORES

# L1 cache

PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD

PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT

PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD

# L2 cache

PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_REFERENCES

PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD

PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT

PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS

PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD

#PRESET,PAPI_L2_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_HIT

#PRESET,PAPI_L2_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_MISS

PRESET,PAPI_L2_DCM,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS

PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD

#PRESET,PAPI_L2_LDH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT

PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS

PRESET,PAPI_L2_TCA,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_REFERENCES,L2_RQSTS:ALL_CODE_RD

PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_REFERENCES

PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD

# L3 cache

PRESET,PAPI_L3_DCA,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS

PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD

PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS

PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS

#PRESET,PAPI_L3_LDH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT

PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS

PRESET,PAPI_L3_TCA,NOT_DERIVED,LLC_REFERENCES

PRESET,PAPI_L3_TCM,NOT_DERIVED,LLC_MISSES

…

I think you should be able to use those for tiger lake as well by adding another line as follows:

CPU,tgx

CPU,icx

PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED:THREAD_P

PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P

PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES

# Loads and stores

…

I am not sure what the name for the tiger lake PMU is so replace tgx with the correct PMU name.

Keep in mind that this might not give you accurate measurements as there might be differences between the two PMUs.

Best, 

Giuseppe

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