wasting time on the 8086.

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Alan Grimes

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Nov 4, 2023, 5:51:59 PM11/4/23
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I've been looking at the 8086 some more despite all rational objections.

The main problem with the chip is that intel was twisting themselves
into a pretzel to fit within the DIP-40 form factor. So the chip has to
do things over a number of clock cycles because the address bus and the
data bus is time multiplexed. Obviously, this is unacceptable for a
high-performance part.

The chip doesn't even have enough pins for the control lines it requires
an 8288 chip to decode them.

I don't fully understand the data bus yet, but it preferred to put the
even-order data on the lower byte and the odd-order data on the upper
byte so a 16 bit transfer would work as you would expect but 8-bit
transfers would be sent to their respective chips. (ram would be
interleaved, each bank would carry either the even or the odd bytes.)
Obviously an unaligned 16 bit transfer would need to be split between
two 8-bit transfers....

The datasheet says that 8-bit peripherals can be connected to either the
upper or lower part of the bus but then that makes me wonder how DMA
would work. I guess 16-bit DMA would be fine but 8-bit DMA would need to
be able to deal with the interleaved memory...  (DMA controller = 8237) 
The same chip is re-used in a 16 bit mode by wiring it to the address
bus a bit differently and adding an external 8-bit register and then
cascaded off the first chip.

I think the machine would need a true 8-bit mode where when a true 8-bit
peripheral needs to use the bus, it ties both halves of the data bus
together and honors the low-order bit of the address bus at the memory
chips. The AD0 pin is masked HOT when the machine is in 16-bit mode.
When the CPU uses the bus in 8-bit mode, it can use just half of the bus
in a false 8-bit mode (or half 16-bit mode). In that mode the AD0 pin
just tells the machine which half is active.

Given how many chips this type of machine requires I'm beginning to
doubt I could fit it all within an EATX form factor. =P

--
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