RISC-V HW Dev

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Srishti Sharma, Tommy Murphy2

Mar 25

How to get firtool for macOS

Any use? * https://github.com/chipsalliance/rocket-chip/issues/3601 * https://github.com/

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How to get firtool for macOS

Any use? * https://github.com/chipsalliance/rocket-chip/issues/3601 * https://github.com/

Mar 25

Srishti Sharma, Tommy Murphy2

Mar 18

How to generate the Verilog file for Instruction cache

Might be worth asking that question here, assuming that it's not already dealt with? * https://

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How to generate the Verilog file for Instruction cache

Might be worth asking that question here, assuming that it's not already dealt with? * https://

Mar 18

Kamer Kırali, … Robert Finch4

Mar 13

I confused about Atomic Instruction

thanks for answer. 13 Mart 2024 Çarşamba tarihinde saat 15:53:28 UTC+3 itibarıyla robf...@gmail.com

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I confused about Atomic Instruction

thanks for answer. 13 Mart 2024 Çarşamba tarihinde saat 15:53:28 UTC+3 itibarıyla robf...@gmail.com

Mar 13

Meet Sangani, … Tommy Murphy4

Feb 29

Why is it required to increment PC by 4bits in RISC Architecture?

The same question was asked here: * https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/

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Why is it required to increment PC by 4bits in RISC Architecture?

The same question was asked here: * https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/

Feb 29

Feb 27

Re: Misoprostol حبوب سايتوتيك تنزيل الدورة - 00971553031846 - انا حامل كيف انزله طريقة اجهض اسقط الحمل انزل

> أعلان | للبيع حبوب سايتوتك في الامارات ابوظبي الشارقه العين دبي تسليم > https://linktr.ee/

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Re: Misoprostol حبوب سايتوتيك تنزيل الدورة - 00971553031846 - انا حامل كيف انزله طريقة اجهض اسقط الحمل انزل

> أعلان | للبيع حبوب سايتوتك في الامارات ابوظبي الشارقه العين دبي تسليم > https://linktr.ee/

Feb 27

Feb 26

How to generate Verilog file for Icache of Rocketchip?

I am working on the instruction cache of rocket chip as a part of my project, but I am not able to

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How to generate Verilog file for Icache of Rocketchip?

I am working on the instruction cache of rocket chip as a part of my project, but I am not able to

Feb 26

Muhammed Furqan

Feb 26

wfi in u-mode when u+s configuration

Hi, I am a little confused about the behavior of wfi in u+s configuration. As spec in section 3.1.6.5

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wfi in u-mode when u+s configuration

Hi, I am a little confused about the behavior of wfi in u+s configuration. As spec in section 3.1.6.5

Feb 26

Srinija Ramichetty, Tommy Murphy2

11/10/23

Error while running Berkeley boot loader

> ./bbl/mtrap.c:130: Error: unrecognized opcode `fence.i', extension `zifencei' required

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Error while running Berkeley boot loader

> ./bbl/mtrap.c:130: Error: unrecognized opcode `fence.i', extension `zifencei' required

11/10/23

Jim Kenua, Valentin Nechayev2

11/10/23

"A" Extension - Lock implementation

hi, Tue, Jan 17, 2023 at 08:12:18, jimkenua wrote about "[hw-dev] "A" Extension - Lock

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"A" Extension - Lock implementation

hi, Tue, Jan 17, 2023 at 08:12:18, jimkenua wrote about "[hw-dev] "A" Extension - Lock

11/10/23

Swarna L Swarna LakshmiNarasimha, Tommy Murphy4

10/27/23

bash: /tools/setup_cclass_new_spike.sh: No such file or directory

You still didn't provide ALL of the sort of info that I mentioned. If you want help then you

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bash: /tools/setup_cclass_new_spike.sh: No such file or directory

You still didn't provide ALL of the sort of info that I mentioned. If you want help then you

10/27/23

8/30/23

Hypervisor support in RISCV

Hello I am trying to implement Hypervisor support in the RISCV CPU that i am working on. The target

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Hypervisor support in RISCV

Hello I am trying to implement Hypervisor support in the RISCV CPU that i am working on. The target

8/30/23

Muhammad Ali Akhtar, Tommy Murphy4

7/9/23

Strange PLIC behaviour in Rocket-Chip

> I have 4 HARTS in my config. > 0x2000 HART 0 Context 0 > 0x2080 HART 0 Context 1 The code

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Strange PLIC behaviour in Rocket-Chip

> I have 4 HARTS in my config. > 0x2000 HART 0 Context 0 > 0x2080 HART 0 Context 1 The code

7/9/23

jagten leo, Valentin Nechayev2

6/14/23

The hardware implementation of Atomic instruction in RISCV and performance differences compared to HTM

hi, > 1. I'm confused with "*registers a reservation set*" in the sentence "LR.

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The hardware implementation of Atomic instruction in RISCV and performance differences compared to HTM

hi, > 1. I'm confused with "*registers a reservation set*" in the sentence "LR.

6/14/23

6/12/23

Understanding Macros and Sending Custom Instructions to RISC-V in Chipyard

I'm working with the Chipyard framework and I'm trying to understand how to use macros and

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Understanding Macros and Sending Custom Instructions to RISC-V in Chipyard

I'm working with the Chipyard framework and I'm trying to understand how to use macros and

6/12/23

Valentin Nechayev, Krste Asanovic2

6/12/23

Reason to select ADD for NOP and MV?

First, if a machine optimizes NOPs at decode, it doesn't really matter which opcode is picked as

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Reason to select ADD for NOP and MV?

First, if a machine optimizes NOPs at decode, it doesn't really matter which opcode is picked as

6/12/23

Charles Papon, … Asutosh Mishra12

6/9/23

Tilelink - ProbeBlock toN while inflight AcquireBlock BtoT

Ahhh ok ^^ > That is why in our implementation slave denies these kind of request. Hmm i think

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Tilelink - ProbeBlock toN while inflight AcquireBlock BtoT

Ahhh ok ^^ > That is why in our implementation slave denies these kind of request. Hmm i think

6/9/23

Asutosh Mishra, Tommy Murphy4

6/1/23

Tilelink spec query: 9.4. TL-UL and TL-UH Messages on Channel A and D

> I have posted my query in https://github.com/chipsalliance/tilelink/issues/5 more than 2 weeks,

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Tilelink spec query: 9.4. TL-UL and TL-UH Messages on Channel A and D

> I have posted my query in https://github.com/chipsalliance/tilelink/issues/5 more than 2 weeks,

6/1/23

Chathura Niroshan

5/16/23

Are there any open-source RISC-V SoC designs that have an IOMMU?

Hi All, I know that the IOMMU specification is fairly new (and not ratified yet). Are there efforts

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Are there any open-source RISC-V SoC designs that have an IOMMU?

Hi All, I know that the IOMMU specification is fairly new (and not ratified yet). Are there efforts

5/16/23

Anupam Kumari, Tommy Murphy2

4/4/23

It really depends on what you intend to do. For example... what hardware (eghttps://riscv.org/

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It really depends on what you intend to do. For example... what hardware (eghttps://riscv.org/

4/4/23

Gabriel L. Somlo, … ilamparithy vijayan3

3/21/23

Rocket: identifying source pin of external interrupt?

Hi , I LIke to have same configuration, can you suggest me how intr works On Friday, May 3, 2019 at

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Rocket: identifying source pin of external interrupt?

Hi , I LIke to have same configuration, can you suggest me how intr works On Friday, May 3, 2019 at

3/21/23

李林, … kr...@sifive.com3

3/15/23

chipyard-SmallBoom-Transplantation

This should be asked over on the Chipyard Google group rather than here, Krste >>>>>

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chipyard-SmallBoom-Transplantation

This should be asked over on the Chipyard Google group rather than here, Krste >>>>>

3/15/23

Gabriel L. Somlo, Tommy Murphy3

2/27/23

Updated rocket build instructions w.r.t. "mill"?

On Mon, Feb 27, 2023 at 05:19:59PM +0000, Tommy Murphy wrote: > What happens if you install `mill`

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Updated rocket build instructions w.r.t. "mill"?

On Mon, Feb 27, 2023 at 05:19:59PM +0000, Tommy Murphy wrote: > What happens if you install `mill`

2/27/23

Manili, … Prof. Michael Taylor21

2/7/23

Is it possible/suitable to design a GPU based on RISC-V

Hi all, I'm really wondering to know about any updates regarding RISC-V/Libre GPUs from 2018? Do

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Is it possible/suitable to design a GPU based on RISC-V

Hi all, I'm really wondering to know about any updates regarding RISC-V/Libre GPUs from 2018? Do

2/7/23

1/30/23

RISCV Formal Interface

hey all, I hope you all doing well. Are there any documents from risv-v org about the riscv formal

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RISCV Formal Interface

hey all, I hope you all doing well. Are there any documents from risv-v org about the riscv formal

1/30/23

Chathura Niroshan, Greg Chadwick3

11/14/22

Memory protection for peripheral memory accesses in RISC-V

Thanks Greg, this was helpful! I will take a look at IOMMU. I know Rocket, BOOM and Black Parrot RISC

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Memory protection for peripheral memory accesses in RISC-V

Thanks Greg, this was helpful! I will take a look at IOMMU. I know Rocket, BOOM and Black Parrot RISC

11/14/22

alejandr...@gmail.com

11/4/22

ECC error handling from Scratchpad

Hi all, I'm developing a Rocket-chip architecture in Chisel with L1caches and a TLRAM on the

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ECC error handling from Scratchpad

Hi all, I'm developing a Rocket-chip architecture in Chisel with L1caches and a TLRAM on the

11/4/22

KaMinTo Channel, FangFei Yang2

8/22/22

RISC-V Virtual Memory attack model

This is platform specific, now there is a Zicbom extension, then you can manage cache. Things like

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RISC-V Virtual Memory attack model

This is platform specific, now there is a Zicbom extension, then you can manage cache. Things like

8/22/22

Sean Halle, … Rahul Behl5

8/19/22

Open Source RVV (Vector Unit) implementations

I find the following very helpful: https://github.com/tenstorrent/riscv-ocelot On Fri, Aug 12, 2022

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Open Source RVV (Vector Unit) implementations

I find the following very helpful: https://github.com/tenstorrent/riscv-ocelot On Fri, Aug 12, 2022

8/19/22

alejandr...@gmail.com, sp...@section5.ch3

7/13/22

Fault injection for ECC demonstration

Thanks for your help. Since I'm developing on an UltraScale, I will try to inject failures

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Fault injection for ECC demonstration

Thanks for your help. Since I'm developing on an UltraScale, I will try to inject failures

7/13/22

Sean Halle, Jerry Zhao2

5/24/22

ECC in Tile link between L2 and Memory Controller

The user field of the TL bundles can be specified to carry arbitrary user data alongside the bundle.

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ECC in Tile link between L2 and Memory Controller

The user field of the TL bundles can be specified to carry arbitrary user data alongside the bundle.

5/24/22

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