Congrats! The Google V8 JavaScript Engine now supports RV32GC.

[Wei Wu (吴伟)]

Hi, everyone

We are glad to share that the RV32GC porting of V8 (the JavaScript
engine of the Chrome browser and Node.js) is merged by the Google
upstream today[1].

The porting has been carried out in a cooperative way as a mentorship
project of RVI and the Linux Foundation[2]. Thanks to the
communication channel provided by the mentorship project (special
thanks to Megan!), people who are willing to contribute to RISC-V
could join together more effectively and easily.

Now V8 can support both 32bit and 64bit backends for RISC-V ISA. The
team from PLCT will maintain for it in long term. Reporting bugs at
GitHub repo site[3] is welcome. We hope this would be a stepping
stone to enable more applications for the 32bit RISC-V world.

[1] https://chromium-review.googlesource.com/c/v8/v8/+/3736732
[2] https://mentorship.lfx.linuxfoundation.org/project/2021e650-c533-4671-afed-bf87c089af09
[3] https://github.com/riscv-collab/v8

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Best wishes,
Wei Wu (吴伟)

[Andrew Waterman]

Great work getting it merged upstream!

Were there any porting challenges unique to RV32?

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[Ren Guo]

Great Job,  Congrats! Let's give more effort to the RV32 Linux world.

[ji qiu]

Hi Andrew, 

Sorry for this late reply due to my vacation. 

It's almost no special challenge for the RV64 to RV32 porting. The most common change is to use something like intptr_t instead of int64 for RV64 and int32 for RV32. The second common change is using lw instead of ld for GPR saving and restore. One thing that need to be treated carefully is that, when dealing with saving and restoring of float point registers, we need to calculate the space separately using size 8 and keep the alignment to 8 byte by paddings. However, in RV64, we just using size 8 for both GPR and FPR and the alignment is always 8.

Besides RV32GC and RV64GC, we had also added the V-extension's JIT support in V8. The most challenge part for the V support is that RISC-V is the first and only one which has an independent vector register file. For X86, ARM, MIPS, they have overlapped or aliased FPR and SIMD registers. So the register allocation for RISCV V-ext is quite different from the other backends in V8.