Differences between software simulator(spike)，C++_based cycle-accurate simulator and Verilog_based simulator

[Yuanrong Wang]

Hi, I am so confused with those three conceptions, can anybody help to explain the differences in detail ?

Many thanks !

[Lennart Benschop]

The Spike simulator is a functional simulator for the RISCV instruction
set. The RISCV specification specifies what each instruction does
functionally (add register r1 and register r2, store the result in r3),
but does not specify how many cycles each instruction takes (or how many
cycles you lose when you have a branch). So Spike does not count those
cycles.

The C++ based cycle accurate simulator is for a specific RISCV
implementation (not the RISCV ISA in general). It does model how many
cycles the processor takes for each instruction in each situation. As it
simulates the hardware in more detail, it is expected to be slower than
Spike. Like Spike (but unlike the Verilog model), you can just compile
the C++ model with a normal compiler and run it as ordinary software, no
expensive simulation tools are required.

Verilog is a hardware description language (not a programming language),
this is: you can use it as an input for synthesis tools,which produce a
netlist (a network of logic gates and their interconnections). This
netlist can be converted to an FPGA (a programmable chip with lots and
lots of logic gates that you can program so they are interconnected in a
specific way) or you can process the netlist further with other tools
into the layout of a real chip. A Verilog design can also be simulated,
but capable Verilog simulators cost a fortune (but some FPGA vendors
provide usable simulators at reduced cost or that come for free if you
buy one of their FPGA boards).

--
Lennart

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[Rene Snajder]

Hi!

I have another question on that topic: 

You mention "the C++ based cycle accurate simulator". Am I correct to assume you

mean "Rocket-Chip"? After reading your message i went out to look if I can get this

running, since performance measures are relevant for my project.

So I checked out this [0] and tried to get it to work. Unfortunately I wasn't successful. 

It builds fine, but whenever I try running anything on it (with proxy kernel) it just 

hangs and does nothing - even the simplest Hello World programs that run fine in 

Spike. The symptoms are pretty much the same as this old stack-exchange post [1]

but the suggested solution (using the riscv-tools version that is linked by the repo)

didn't make any difference for me.

Anyways, is this even the right project if I want to do cycle accurate performance 

measurements?

Thanks,

Rene

[0] https://github.com/ucb-bar/rocket-chip

[1] http://stackoverflow.com/questions/31679920/rocket-and-chisel-nothing-happening-in-the-emulator-for-assembler-tests

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/1458543230.1408.16.camel%40xs4all.nl.