Clarification on setting software breakpoint

[dharan G]

Hi all,
Could someone explain how the ebreak instruction reaches the hart when software breakpoint (break command) is given in debugger (gdb) terminal while debugging the riscv hart.

Thanks in Advance,

Dharani Shankar.

[Tommy Murphy]

The debugger saves the instruction at the breakpoint address, temporarily replaces it with a breakpoint instruction and restores the original instruction when the breakpoint fires or the target otherwise reverts to debug halt. This is general standard practice and not specific to RISC-V.

[Srihari Chadalawada]

Hii,

Is it possible for replacing the instruction at breakpoint address if the memory is of flash type. If possible can you explain how it is possible.

Thanks in advance,

Srihari

[merle w]

gdb needs to record old instructions and then write ebreak. In the debugging specification 0.11, it is realized by writing instructions in write Debug RAM; in the debugging specification 0.13, it is realized by abstract commands of the Access Memory type

Under normal circumstances, debugging in flash needs to be implemented through hardware breakpoints. In the debugging specification 0.13, trigger can be used to implement hardware breakpoints

[Tommy Murphy]

In that case you'd normally use a hardware breakpoint/trigger. Some targets (e.g. some Arm Cortex targets via the Flash Patch and Breakpoint Unit) effectively provide a mechanism to use software breakpoints for code in read only memory. Some other targets may allow reprogramming flash on the fly for software breakpointing but that would be slow and cause flash wear. In general it's more normal to use hardware breakpoints for code in flash/read only memory.

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From: Srihari Chadalawada <chadalawad...@gmail.com>
Sent: Friday, December 24, 2021 9:17:38 AM
To: RISC-V SW Dev <sw-...@groups.riscv.org>
Cc: tommy_...@hotmail.com <tommy_...@hotmail.com>; dhara...@gmail.com <dhara...@gmail.com>
Subject: Re: [sw-dev] Clarification on setting software breakpoint

 

[Jim Wilson]

On Fri, Dec 24, 2021 at 1:17 AM Srihari Chadalawada <chadalawad...@gmail.com> wrote:

Is it possible for replacing the instruction at breakpoint address if the memory is of flash type. If possible can you explain how it is possible.

There is no one actively working on gdb, and it has rather limited support.  It only supports software breakpoints, and if you can't write an ebreak to the target address then you can't set a breakpoint.  But openocd has active development and much better support.  It has hardware breakpoint support, at least on SiFive cores.  So you probably need to use gdb with openocd, rather than just gdb alone.  Or pay someone to do a lot of gdb work to improve it.

Jim

 

[Sober Liu]

Per my understanding, you can set memory type for an area as read-only for GDB. Then gdb will use HW breakpoint if PC locates in the area.

 

From: Jim Wilson <jim.wil...@gmail.com>
Sent: Saturday, December 25, 2021 2:53 AM
To: Srihari Chadalawada <chadalawad...@gmail.com>
Cc: RISC-V SW Dev <sw-...@groups.riscv.org>; tommy_...@hotmail.com <tommy_...@hotmail.com>; dhara...@gmail.com <dhara...@gmail.com>
Subject: Re: [sw-dev] Clarification on setting software breakpoint

 

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[Tommy Murphy]

> Per my understanding, you can set memory type for an area as read-only for GDB. Then gdb will use HW breakpoint if PC locates in the area.

 

That's correct for OpenOCD but not when using gdb "directly" on the RISC-V platform or via a non OpenOCD gdb server/stub according to what Jim posted earlier.