An open-source CPU integration RVV support in gem5 from PLCT

[Yin Zhang]

Hi all,

FYI, we PLCT give a public implementation of  RVV support in gem5.

url: https://github.com/plctlab/plct-gem5.

rvv-cpu branch.

The implementation is CPU integrated, using micro instructions to implement vector memory access and operations.

The current version (commit ba93d3e0) already works on AtomicSimpleCPU、TimingSimpleCPU、MinorCPU in gem5, and partially works on O3CPU.  There is a problem with mask related instructions on O3CPU, which is being repaired.

We have supported ~100 frequently-used vector instructions, accounting for about 15% of the total instructions. The implemented instructions have passed the tests of SEW from 8 to 64 and LMUL from 1/8 to 8. Due to the lack of test sets for RVV at present, we temporarily use [riscv-vector-tests](https://github.com/huxuan0307/riscv-vector-tests) developed by one of our contributors, Hu Xuan, to perform the basic functional tests.

Future works:

- Improve O3CPU support.

- Support more RVV instructions.

- Add dynamic latency support and improve OpClass (at present, all vector instructions are put into VectorDummyOp, and latency is 1).

- Complete spec support. Including vill, vstart, tail end processing vta, vma, etc.

You are welcome to try out and put forward your opinions. We also welcome cooperative development. Please be free to contact us.

Regards,

Yin Zhang (张尹)