Cycle accurate simulator for RISC-V vector instructions
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zazad
Sep 4, 2021, 6:38:13 PM9/4/21
to RISC-V SW Dev
Hi all,
Is there any publicly available cycle-accurate simulator for risc-v vector extension with MMU support(e.g., capable of handling a page fault in the middle of vector memory instruction)?
I found that Gem5 supports vectors for risc-v, but it is only in the SE mode so no virtual memory support .
Thank you!
Is there any publicly available cycle-accurate simulator for risc-v vector extension with MMU support(e.g., capable of handling a page fault in the middle of vector memory instruction)?
I found that Gem5 supports vectors for risc-v, but it is only in the SE mode so no virtual memory support .
Thank you!
Bruce Hoult
Sep 4, 2021, 8:19:23 PM9/4/21
to zazad, RISC-V SW Dev
A cycle-accurate simulation implies simulating some particular concrete implementation of the specifications. There are not yet any publicly available implementations of the RISC-V Vector extension [1]. No doubt companies developing such implementations have their own simulators internally, but they are not sharing them (and would be unlikely to after the chips are released).
No doubt there will eventually be Open Source implementations of the V extension, but it might be a while.
It is possible that some implementations might transparently handle a page fault in the middle of a vector load or store instruction, but I would expect most would abort the instruction and set the VSTART CSR to reflect the amount already processed so that the instruction could be re-run and use the freshly loaded page once the page fault has been handled.
You could just buy a Nezha board and experiment with that instead of a simulator. It's $99 and supports Linux and virtual memory.
[1] except the Allwinner D1 chip, available on the "Nezha" evaluation board, which implements an older (0.7.1) draft version of the RISC-V vector spec.
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Zahra Azad
Sep 5, 2021, 4:08:38 PM9/5/21
to Bruce Hoult, RISC-V SW Dev
Thank you for the information Bruce!
Jerin Joy
Mar 4, 2022, 1:57:07 PM3/4/22
to RISC-V SW Dev, Bruce Hoult, zazad
Hi,
We (Rivos) are working on adding RVV support to Gem5. I had sent an email out yesterday about the initial changes that we have released publicly:
Our goal is to contribute back to the open source projects we're leveraging so we're making our changes public.
We'd love to collaborate if you are looking at implementing RVV support in Gem5.
Jerin
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