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Buildroot RV32IMA_ZICSR_ZIFENCEI
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Rajnesh Joshi
Jul 12, 2024, 11:54:27 PM7/12/24
to RISC-V SW Dev
Hello,
I cannot get Buildroot to create a 32-bit RISCV Linux Image because it says 'zicsr' or 'zifencei' instructions are missing.
defconfig:
I have tried the above (auto-generated using make savedefconfig). I have also tried to make the `BR2_EXTRA_GCC_CONFIG_OPTION=--with-arch=rv32ima_zicsr_zifencei` as well and that did not work.
I manually added the following line `BR2_TOOLCHAIN_GCC_AT_LEAST_12 = y` to the end of the defconfig as the follow lines are in `arch.mk.riscv32`
```
# Starting from gcc 12.x, csr and fence instructions have been
# separated from the base I instruction set, and special -march
# suffixes are needed to enable their support. In Buildroot, we assume
# all RISC-V cores that support Linux implement those instructions, so
# we unconditionally enable those extensions.
ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
endif
I cannot get Buildroot to create a 32-bit RISCV Linux Image because it says 'zicsr' or 'zifencei' instructions are missing.
defconfig:
BR2_riscv=y
BR2_riscv_custom=y
BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_RVA=y
BR2_RISCV_32=y
# BR2_RISCV_USE_MMU is not set
BR2_KERNEL_HEADERS_6_1=y
BR2_GCC_VERSION_12_X=y
BR2_EXTRA_GCC_CONFIG_OPTIONS="-march=rv32ima_zicsr_zifencei"
BR2_ENABLE_DEBUG=y
BR2_ENABLE_RUNTIME_DEBUG=y
BR2_ROOTFS_OVERLAY="board/litex_vexriscv/rootfs_overlay"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_GIT=y
BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/litex-hub/linux.git"
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="10ab1c7354a3d0e3b0d04ff0850a0f5eff0639bd"
BR2_LINUX_KERNEL_PATCH="patches"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="board/litex_vexriscv/linux.config"
BR2_TARGET_ROOTFS_CPIO=y
# BR2_TARGET_ROOTFS_TAR is not set
I manually added the following line `BR2_TOOLCHAIN_GCC_AT_LEAST_12 = y` to the end of the defconfig as the follow lines are in `arch.mk.riscv32`
```
# Starting from gcc 12.x, csr and fence instructions have been
# separated from the base I instruction set, and special -march
# suffixes are needed to enable their support. In Buildroot, we assume
# all RISC-V cores that support Linux implement those instructions, so
# we unconditionally enable those extensions.
ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
endif
```
That did not work either. How do I get that automatically generated into my defconfig through the make menuconfig options, I cannot find how to set that? Shouldn't that automatically be set since my gcc is >= 12.0?
RJ
That did not work either. How do I get that automatically generated into my defconfig through the make menuconfig options, I cannot find how to set that? Shouldn't that automatically be set since my gcc is >= 12.0?
RJ
Tommy Murphy
Jul 16, 2024, 7:01:07 AM7/16/24
to Rajnesh Joshi, RISC-V SW Dev
Weren't there patches to address this issue a while back? E.g.:
Message has been deleted
Rajnesh Joshi
Jul 19, 2024, 7:51:17 AM7/19/24
to RISC-V SW Dev, tommy_...@hotmail.com, Rajnesh Joshi
The patch does not seem to be working
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