Understanding vector indexed store vsuxei32 in RISCV-V riscv vector instructions on spike simulator

[Balaji Chegu]

I am trying to understand vector indexed store instructions. Here is the sample code that I tried.

The source array has elements `0xabc0,0xabc1,0xabc2,0xabc3`. With the indexing 3, 2, 1, 0, I expected it to print `0xabc3,0xabc2,0xabc1,0xabc0` but I get
**Store/AMO access fault!**

But when indexes are given `int32_t indexes[NELMS] = {0,0,0,0};` I get `abc3 0 0 0` as output.  I am unable to understand how the instruction is picking the indexes.

```c
#include <stdio.h>
#include <stdint.h>
#define NELMS 4

void scg(int32_t *dest, int32_t *base_addr, int32_t *offsets, int32_t elements) {
    int32_t vl = 0;
    asm ("vsetvli %0, %1, e32, m1\n" : "=r"(vl) : "r"(elements));
 
    for(int32_t i=0; i<vec_elems;i+=vl){
        asm ("vle32.v v2, (%0)\n" : : "r"(base_addr+i));
        asm ("vle32.v v3, (%0)\n" : : "r"(offsets));
        //asm ("vse32.v v2, (%0)\n" : : "r"(dest+i));
        asm ("vsoxei32.v v2, (%0), v3\n" : :"r"(dest+i));
    }

}


int main() {
    int elements = NELMS;

    int32_t src[NELMS] = {  0xabc0,
                            0xabc1,
                            0xabc2,
                            0xabc3};                            

    int32_t indexes[NELMS] = {3,2,1,0};
    int32_t dst[NELMS] = {0};

    scg(dst, src, indexes, elements);

    for (int i = 0; i < elements; i++) {
        printf("%x ", dst[i]);
    }

    return 0;

}
```

[Hugues de Lassus]

From the RISC-V V spec, section 7.2 and 7.6:

"The vector offset operand is treated as a vector of byte-address offsets."

"The assembler syntax for indexed loads and stores uses eix instead of ex to indicate the statically encoded EEW is of the index not the data."

Your indices needs to be scaled by 4 bytes per int32_t, so {12, 8, 4, 0}. I suppose the access fault is due to misaligned memory write.

Cheers,

Hugues

[Balaji Chegu]

Thanks Hugues. It works now.