Forgive my ignorance; I've never used pre-made bitstreams before, and
certainly have never used Vivado before either. But, in my (limited!)
experience, a bitstream is the **final** result of the synthesis
process. As far as I know, once you have a bitstream, the most you
can do is change the contents of block RAM; the digital logic itself
will be frozen.
Can a tool like Vivado allow you to "bolt on" to a pre-existing
bitstream, so as to include your own memory controllers and the like?
(Feel free to answer off-list if you want; I recognize this is
If not, it seems like the bitstream you get is fixed function, and
should already include a memory controller if it's been configured to
grant access to DDR RAM.
Thanks for clarifications from Vivado users.
On Wed, Aug 29, 2018 at 5:25 PM Bruce Hoult <bruce...@sifive.com
> I'm pretty sure the answer is that E31/E51 bitstreams for the Arty are intended as evaluation for the corresponding cores in microcontroller SoCs, and so have just the 16 - 64 KB of scratchpad SRAM they will have in an SoC (and which is provided within the FPGA on the Arty).
> Vivado comes with a DDR controller intended for use with their Microblaze core. I don't actually know whether the license allows it to be used with other soft cores, though probably someone skilled with FPGAs could physically make it work.
> On Wed, Aug 29, 2018 at 10:09 AM, Tommy Murphy <tommy_...@hotmail.com
>> Have you checked the SiFive forums in case this is answered there?
>> You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
>> To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+un...@groups.riscv.org
> You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+un...@groups.riscv.org
> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CAP8PnuQnPm7cdD3b_Ygczgv%2Bp%3DQ_Aayy8JRX2QtMeR2B0fzJTA%40mail.gmail.com
Samuel A. Falvo II