How to use the ddr3 Ram

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Andreas Dachsberger

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Aug 29, 2018, 9:13:42 AM8/29/18
to RISC-V SW Dev
Hi,
I want to use the external ddr3 Ram on my digilent arty board.
I use the freedom-e-sdk. What I'm missing is a memory controller for the ddr3 Ram.
Is there maybe one already included in the freedom-e-sdk?
If somebody could explain me how to make it work, I would be very thankful.
Thanks in advance!

Tommy Murphy

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Aug 29, 2018, 1:09:12 PM8/29/18
to RISC-V SW Dev
Have you checked the SiFive forums in case this is answered there?

Bruce Hoult

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Aug 29, 2018, 8:25:05 PM8/29/18
to Tommy Murphy, RISC-V SW Dev
I'm pretty sure the answer is that E31/E51 bitstreams for the Arty are intended as evaluation for the corresponding cores in microcontroller SoCs, and so have just the 16 - 64 KB of scratchpad SRAM they will have in an SoC (and which is provided within the FPGA on the Arty).

Vivado comes with a DDR controller intended for use with their Microblaze core. I don't actually know whether the license allows it to be used with other soft cores, though probably someone skilled with FPGAs could physically make it work.

On Wed, Aug 29, 2018 at 10:09 AM, Tommy Murphy <tommy_...@hotmail.com> wrote:
Have you checked the SiFive forums in case this is answered there?

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Samuel Falvo II

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Aug 29, 2018, 10:06:07 PM8/29/18
to Bruce Hoult, Tommy Murphy, RISC-V SW Dev
Forgive my ignorance; I've never used pre-made bitstreams before, and
certainly have never used Vivado before either. But, in my (limited!)
experience, a bitstream is the **final** result of the synthesis
process. As far as I know, once you have a bitstream, the most you
can do is change the contents of block RAM; the digital logic itself
will be frozen.

Can a tool like Vivado allow you to "bolt on" to a pre-existing
bitstream, so as to include your own memory controllers and the like?
(Feel free to answer off-list if you want; I recognize this is
off-topic.)

If not, it seems like the bitstream you get is fixed function, and
should already include a memory controller if it's been configured to
grant access to DDR RAM.

Thanks for clarifications from Vivado users.

On Wed, Aug 29, 2018 at 5:25 PM Bruce Hoult <bruce...@sifive.com> wrote:
>
> I'm pretty sure the answer is that E31/E51 bitstreams for the Arty are intended as evaluation for the corresponding cores in microcontroller SoCs, and so have just the 16 - 64 KB of scratchpad SRAM they will have in an SoC (and which is provided within the FPGA on the Arty).
>
> Vivado comes with a DDR controller intended for use with their Microblaze core. I don't actually know whether the license allows it to be used with other soft cores, though probably someone skilled with FPGAs could physically make it work.
>
> On Wed, Aug 29, 2018 at 10:09 AM, Tommy Murphy <tommy_...@hotmail.com> wrote:
>>
>> Have you checked the SiFive forums in case this is answered there?
>>
>> https://forums.sifive.com/
>>
>> --
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Samuel A. Falvo II

Bruce Hoult

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Aug 29, 2018, 10:39:14 PM8/29/18
to Samuel Falvo II, Tommy Murphy, RISC-V SW Dev
Yes, of course you are correct. The RTL that produces the bitstream is also available, though in sufficiently obfuscated form that you'd be better off starting from a fully open-source core such as rocket-chip or picorv32 if you want to add support for DDR. As I said, the FPGA bitstreams SiFive provides are for product evaluation, not hacking on.

The freedom-e-sdk packaging of the GNU toolchain and other useful tools is of course welcome for use by anyone.

So, really, I guess the original question (and my reply) is a bit of a non-sequitur. Freedom-e-sdk doesn't actually have anything to do with CPU cores or interfacing them to other hardware and it was only an assumption on my part that Andreas was using it with a SiFive core.

On Wed, Aug 29, 2018 at 7:05 PM, Samuel Falvo II <sam....@gmail.com> wrote:
Forgive my ignorance; I've never used pre-made bitstreams before, and
certainly have never used Vivado before either.  But, in my (limited!)
experience, a bitstream is the **final** result of the synthesis
process.  As far as I know, once you have a bitstream, the most you
can do is change the contents of block RAM; the digital logic itself
will be frozen.

Can a tool like Vivado allow you to "bolt on" to a pre-existing
bitstream, so as to include your own memory controllers and the like?
(Feel free to answer off-list if you want; I recognize this is
off-topic.)

If not, it seems like the bitstream you get is fixed function, and
should already include a memory controller if it's been configured to
grant access to DDR RAM.

Thanks for clarifications from Vivado users.

On Wed, Aug 29, 2018 at 5:25 PM Bruce Hoult <bruce...@sifive.com> wrote:
>
> I'm pretty sure the answer is that E31/E51 bitstreams for the Arty are intended as evaluation for the corresponding cores in microcontroller SoCs, and so have just the 16 - 64 KB of scratchpad SRAM they will have in an SoC (and which is provided within the FPGA on the Arty).
>
> Vivado comes with a DDR controller intended for use with their Microblaze core. I don't actually know whether the license allows it to be used with other soft cores, though probably someone skilled with FPGAs could physically make it work.
>
> On Wed, Aug 29, 2018 at 10:09 AM, Tommy Murphy <tommy_...@hotmail.com> wrote:
>>
>> Have you checked the SiFive forums in case this is answered there?
>>
>> https://forums.sifive.com/
>>
>> --
>> You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
>> To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+unsubscribe@groups.riscv.org.

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>> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/55fc2b31-ec27-46a2-9944-cc520a9d9a71%40groups.riscv.org.
>
>
> --
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Michael Clark

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Aug 30, 2018, 10:58:45 AM8/30/18
to Andreas Dachsberger, RISC-V SW Dev
You can check out the RTL for the e300devkit here:


and modify the e300artydevkit Config to add a memory interface. It you sift through rocket-chip, fpga-shells and the unleashed Config you’ll see how the memory interface is wired to the core. The memory controller on the Arty has a 16-bit bus so that config might not have been tested. You will undoubtedly need to write a little Chisel to connect it all up. Not impossible. It’s in Scala so it’s kinda like writing software, just synthesis takes longer than a typical compiler.

Here’s the Arty MIG resources:


You could add the Ethernet too. I’m not sure how many LUTs the additional IPs take up. Do make a PR when you’re done.

Michael

Tetsuya Horie

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Sep 6, 2018, 4:13:48 AM9/6/18
to RISC-V SW Dev, andreas.d...@gmail.com
I ported Freedom U500 to Nexys4 DDR. 


Below is commit log.


Most important class for DDR is nexys4ddrmig.


I modified <ModuleName> in XML, and id field, such as val s_axi_awid = Bits(INPUT,1) etc., in Scala class.

2018年8月30日木曜日 23時58分45秒 UTC+9 Michael Clark:

Bruce Hoult

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Sep 6, 2018, 4:48:59 AM9/6/18
to Tetsuya Horie, RISC-V SW Dev, andreas.d...@gmail.com
Awesome!

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Salman Sheikh

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Jan 23, 2019, 2:35:09 PM1/23/19
to RISC-V SW Dev, andreas.d...@gmail.com
There is a reset pin on the Arty35 DDR that I don't see on the Nexys4 DDR schematic. How should I connect that? I think I got all the files created for the Arty35 and created another Makefile.e300artyddrdevkit file
and got the

make -f Makefile.e300artyddrdevkit verilog

compiled and now I am testing whether the

make -f Makefile.e300artyddrdevkit mcs

will work correctly.
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