RISC-V Assembly Programmer's handbook

[ataowa]

Hello,

 Is there a "RISC-V Assembly Programmer's handbook" available?

 Could someone please point to it?

 If a finalized handbook is not available yet, then any pointers which can help would also be helpful.

Thanks,

ataowa

[Nicolás Ojeda Bär]

Hi ataowa,

There is something (not much) in Chapter 20 of the RISC-V spec.

Best wishes,

Nicolas

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[ataowa]

Thanks Nicolas,

 I have been referring to that. Calling convention is helpful but It just is not sufficient in terms of different instructions arguments directives etc.

Regards,

Nitin

On Tuesday, May 23, 2017 at 3:02:46 PM UTC+5:30, n.oje.bar wrote:

Hi ataowa,

There is something (not much) in Chapter 20 of the RISC-V spec.

Best wishes,

Nicolas

On Tue, May 23, 2017 at 11:30 AM, ataowa <ataowa....@gmail.com> wrote:

Hello,

 Is there a "RISC-V Assembly Programmer's handbook" available?

 Could someone please point to it?

 If a finalized handbook is not available yet, then any pointers which can help would also be helpful.

Thanks,

ataowa

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[Michael Clark]

Hi Nitin,

I have a small doc, however it is very much a work in progress and is not what I would call a complete guide however it lists all assembler directives that I have discovered from reversing GCC output:

https://github.com/rv8-io/rv8/blob/master/doc/src/asm.md

There are also some complete but small assembly language programs in the test directory (the .S files):

https://github.com/rv8-io/rv8/tree/master/src/test

Michael

Sent from my iPhone

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[Megan Wachs]

Michael, great doc!

 I was recently pointed to the relevant code, which is pretty straightforward if you just want the list of pseudo ops binutils would recognize (you may have them all already):

https://github.com/riscv/riscv-binutils-gdb/blob/riscv-next/opcodes/riscv-opc.c

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/049C4A9A-CFE7-4897-954C-FE34481636EB%40mac.com.

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Engineer | SiFive, Inc 

300 Brannan St, Suite 403 

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me...@sifive.com

[ataowa]

Thank you Michael,

  This is good reference.

Warm regards!

[Michael Clark]

Hi Megan,

Yes. The source is pretty straightforward. I spent a little time reading parts of binutils (mostly to do with relocs), writing small C programs and running objdump on the resulting objects to understand the transform from C to RISC-V asm as well as the emitted ELF relocations. I’m still discovering new things…

I didn’t know we can use “move” instead of “mv”, “jump” instead of “j” and I’ve just spotted “unimp” i.e. the canonical illegal instruction.

What’s not listed in riscv-op.c but is somewhere else in binutils is the list of dot prefixed assembler directives. I recently discovered .2byte, .4byte and .8byte which are not in the list I assembled. I must add them. I initially thought they were synonyms for .half, .word and .dword however it appears that they the numeric versions emit unaligned data:

- https://reviews.llvm.org/D4582

Michael.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CAKnTnFTNMkx7yqtg51Ebxn4s-1j1Zp7f%2BjpH%3DHyUTFUSiMg7uw%40mail.gmail.com.

[Stefan O'Rear]

On Tue, May 23, 2017 at 7:15 AM, Michael Clark <michae...@mac.com> wrote:
> What’s not listed in riscv-op.c but is somewhere else in binutils is the
> list of dot prefixed assembler directives. I recently discovered .2byte,
> .4byte and .8byte which are not in the list I assembled. I must add them. I
> initially thought they were synonyms for .half, .word and .dword however it
> appears that they the numeric versions emit unaligned data:

https://sourceware.org/binutils/docs/as/Pseudo-Ops.html

although 2byte etc seem to be missing.

-s

[Palmer Dabbelt]

The RISC-V-specific pseudo ops (which start with a "." prefix, as opposed to
assembler aliases which look like instructions) live in gas/config/tc-riscv.c

static const pseudo_typeS riscv_pseudo_table[] =
{
/* RISC-V-specific pseudo-ops. */
{"option", s_riscv_option, 0},
{"half", cons, 2},
{"word", cons, 4},
{"dword", cons, 8},
{"dtprelword", s_dtprel, 4},
{"dtpreldword", s_dtprel, 8},
{"bss", s_bss, 0},
{"uleb128", s_riscv_leb128, 0},
{"sleb128", s_riscv_leb128, 1},

{ NULL, NULL, 0 },
};

with ".option" having a staticly defined list of arguments

static void
s_riscv_option (int x ATTRIBUTE_UNUSED)
{
char *name = input_line_pointer, ch;

while (!is_end_of_line[(unsigned char) *input_line_pointer])
++input_line_pointer;
ch = *input_line_pointer;
*input_line_pointer = '\0';

if (strcmp (name, "rvc") == 0)
riscv_set_rvc (TRUE);
else if (strcmp (name, "norvc") == 0)
riscv_set_rvc (FALSE);
else if (strcmp (name, "pic") == 0)
riscv_opts.pic = TRUE;
else if (strcmp (name, "nopic") == 0)
riscv_opts.pic = FALSE;
else if (strcmp (name, "relax") == 0)
riscv_opts.relax = TRUE;
else if (strcmp (name, "norelax") == 0)
riscv_opts.relax = FALSE;
else if (strcmp (name, "push") == 0)
{
struct riscv_option_stack *s;

s = (struct riscv_option_stack *) xmalloc (sizeof *s);
s->next = riscv_opts_stack;
s->options = riscv_opts;
riscv_opts_stack = s;
}
else if (strcmp (name, "pop") == 0)
{
struct riscv_option_stack *s;

s = riscv_opts_stack;
if (s == NULL)
as_bad (_(".option pop with no .option push"));
else
{
riscv_opts = s->options;
riscv_opts_stack = s->next;
free (s);
}
}
else
{
as_warn (_("Unrecognized .option directive: %s\n"), name);
}
*input_line_pointer = ch;
demand_empty_rest_of_line ();
}

Additionally, the generic ELF pseudo ops live in gas/config/obj-elf.c

static const pseudo_typeS elf_pseudo_table[] =
{
{"comm", obj_elf_common, 0},
{"common", obj_elf_common, 1},
{"ident", obj_elf_ident, 0},
{"lcomm", obj_elf_lcomm, 0},
{"local", obj_elf_local, 0},
{"previous", obj_elf_previous, 0},
{"section", obj_elf_section, 0},
{"section.s", obj_elf_section, 0},
{"sect", obj_elf_section, 0},
{"sect.s", obj_elf_section, 0},
{"pushsection", obj_elf_section, 1},
{"popsection", obj_elf_popsection, 0},
{"size", obj_elf_size, 0},
{"type", obj_elf_type, 0},
{"version", obj_elf_version, 0},
{"weak", obj_elf_weak, 0},

/* These define symbol visibility. */
{"internal", obj_elf_visibility, STV_INTERNAL},
{"hidden", obj_elf_visibility, STV_HIDDEN},
{"protected", obj_elf_visibility, STV_PROTECTED},

/* These are used for stabs-in-elf configurations. */
{"line", obj_elf_line, 0},

/* This is a GNU extension to handle symbol versions. */
{"symver", obj_elf_symver, 0},

/* A GNU extension to change subsection only. */
{"subsection", obj_elf_subsection, 0},

/* These are GNU extensions to aid in garbage collecting C++ vtables. */
{"vtable_inherit", (void (*) (int)) &obj_elf_vtable_inherit, 0},
{"vtable_entry", (void (*) (int)) &obj_elf_vtable_entry, 0},

/* A GNU extension for object attributes. */
{"gnu_attribute", obj_elf_gnu_attribute, 0},

/* These are used for dwarf. */
{"2byte", cons, 2},
{"4byte", cons, 4},
{"8byte", cons, 8},
/* These are used for dwarf2. */
{ "file", (void (*) (int)) dwarf2_directive_file, 0 },
{ "loc", dwarf2_directive_loc, 0 },
{ "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },

/* We need to trap the section changing calls to handle .previous. */
{"data", obj_elf_data, 0},
{"offset", obj_elf_struct, 0},
{"struct", obj_elf_struct, 0},
{"text", obj_elf_text, 0},

{"tls_common", obj_elf_tls_common, 0},

/* End sentinel. */
{NULL, NULL, 0},
};

I think that should be the full list of things you can put into our assembler.

Thanks for documenting this! If you'd like, we can provide you with some sort
of hosting on the RISC-V github (much like the PS ABI document has).

On Tue, 23 May 2017 07:15:43 PDT (-0700), michae...@mac.com wrote:
> Hi Megan,
>
> Yes. The source is pretty straightforward. I spent a little time reading parts of binutils (mostly to do with relocs), writing small C programs and running objdump on the resulting objects to understand the transform from C to RISC-V asm as well as the emitted ELF relocations. I’m still discovering new things…
>
> I didn’t know we can use “move” instead of “mv”, “jump” instead of “j” and I’ve just spotted “unimp” i.e. the canonical illegal instruction.
>
> What’s not listed in riscv-op.c but is somewhere else in binutils is the list of dot prefixed assembler directives. I recently discovered .2byte, .4byte and .8byte which are not in the list I assembled. I must add them. I initially thought they were synonyms for .half, .word and .dword however it appears that they the numeric versions emit unaligned data:
>

> - https://reviews.llvm.org/D4582 <https://reviews.llvm.org/D4582>

>
> Michael.
>
>> On 24 May 2017, at 1:59 AM, Megan Wachs <me...@sifive.com> wrote:
>>
>> Michael, great doc!
>>
>> I was recently pointed to the relevant code, which is pretty straightforward if you just want the list of pseudo ops binutils would recognize (you may have them all already):
>>

>> https://github.com/riscv/riscv-binutils-gdb/blob/riscv-next/opcodes/riscv-opc.c <https://github.com/riscv/riscv-binutils-gdb/blob/riscv-next/opcodes/riscv-opc.c>

>>
>>
>> On Tue, May 23, 2017 at 09:22 Michael Clark <michae...@mac.com <mailto:michae...@mac.com>> wrote:
>> Hi Nitin,
>>
>> I have a small doc, however it is very much a work in progress and is not what I would call a complete guide however it lists all assembler directives that I have discovered from reversing GCC output:
>>

>> https://github.com/rv8-io/rv8/blob/master/doc/src/asm.md <https://github.com/rv8-io/rv8/blob/master/doc/src/asm.md>

>>
>> There are also some complete but small assembly language programs in the test directory (the .S files):
>>

>> https://github.com/rv8-io/rv8/tree/master/src/test <https://github.com/rv8-io/rv8/tree/master/src/test>

>>
>> Michael
>>
>> Sent from my iPhone
>>

>> On 23/05/2017, at 10:36 PM, ataowa <ataowa....@gmail.com <mailto:ataowa....@gmail.com>> wrote:
>>
>>> Thanks Nicolas,
>>> I have been referring to that. Calling convention is helpful but It just is not sufficient in terms of different instructions arguments directives etc.
>>>
>>> Regards,
>>> Nitin
>>>
>>> On Tuesday, May 23, 2017 at 3:02:46 PM UTC+5:30, n.oje.bar wrote:
>>> Hi ataowa,
>>>
>>> There is something (not much) in Chapter 20 of the RISC-V spec.
>>>
>>> Best wishes,
>>> Nicolas
>>>
>>>
>>> On Tue, May 23, 2017 at 11:30 AM, ataowa <ataowa....@gmail.com <>> wrote:
>>> Hello,
>>> Is there a "RISC-V Assembly Programmer's handbook" available?
>>> Could someone please point to it?
>>> If a finalized handbook is not available yet, then any pointers which can help would also be helpful.
>>>
>>> Thanks,
>>> ataowa
>>>
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>>
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>> --
>> Megan A. Wachs
>> Engineer | SiFive, Inc
>> 300 Brannan St, Suite 403
>> San Francisco, CA 94107

>> me...@sifive.com <mailto:me...@sifive.com>

>>
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[Michael Clark]

Hi Palmer,

OK. I’ll go through the source and find the directives I’ve missed.

Yes. We could perhaps use the asm.md file as a starting point for riscv-asm-guide (or some appropriate name) on the riscv github. Feel free to treat the content there as public domain. If you create a repo I can make a pull request.

Regards,
Michael.

> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/mhng-22fbc7b5-c078-468b-8350-5e049dba7988%40palmer-si-x1c4.

[Palmer Dabbelt]

Great! Here's a skeleton patterned off the riscv-elf-psabi-doc repository

https://github.com/riscv/riscv-asm-manual

Feel free to structure it however you want. For the PS ABI document we first
made a big outline, which allows people to fill in sections in parallel.

If you find deficiencies in the binutils documentation then feel free to either
submit a patch (you can mail it to binutils and "To:" me, or PR it to github)
or an issue (on the binutils github).

Thanks for doing this!

> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/EDDB2D8D-3494-4899-B3D8-93AE5191FFBA%40mac.com.

[Po-wei Huang]

hi,

Folllowing on this topic, is there anyone still works on a complete risc-v assembly programming manual?

There are at least three seperate doc:

1.some in the user spec.

2. That one made by Palmer.

3. One doc on rv8 website.

Trying to teach other about riscv assembly programming, but couldn't find a complete manual for this.

I guess courses about riscv in college also needs this. Could I ask about how do people get over this?

Thanks,

Powei

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[Michael Clark]

Hi Po-wei,

The intention is that the content on the rv8 asm page will be merged with riscv-asm-manual. The goal of the rv8 page was to experiment with GitHub pages presentation as GitHub pages is not enabled on the riscv-asm-manual repo. I’ll add it to my todo list to make a pull request to sync these docs.

I also noticed Alex recently mentioned his work on documenting compiler flags and there is the pre-existing work on documenting the ABI (calling convention and ELF relocations), all in different repos with essentially one file.

There is also an ISA reference on the rv8 page, which is not intended to supplant the specification, rather the goal was to show the assembly language syntax as this is relevant for the assembly guide as the assembly language form of the instructions is currently missing from the specification. There are also many gaps in the currently assembly language docs as we jump straight into assembly language but we don’t show assembler and linker invocations.

Some thought has to be put into the overall structure of the docs. We could also document linker scripts and how to achieve various linkage scenarios with newlib, libgloss and libnosys plus there are Liviu’s docs on RISC-V compiler defines that are also relevant to both GCC and LLVM. The compiler defines could potentially go in the compiler docs along with the flags.

Given there are various and sundry docs, one wonders if we should instead have a single github.com/riscv/riscv-docs repo given most of these existing repos have a single file? e.g.

- psabi.md
- assembler.md
- compiler.md
- isa.md

There is also the issue of presentation and the final form for these docs i.e. Markdown/reStructuredText/LaTeX. The last time we discussed this, the idea was to use Markdown for information collection and that the documentation may end up in a different form for presentation as the default rendering by GitHub for Markdown content is less than ideal. We could use restructured text or possibly even LaTeX or both…

LLVM uses Sphinx which I believe is restructured text. I would be keen to try out Sphinx at some point as it can also be used to build PDF docs:

- http://llvm.org/docs/

I don’t mind to work with Palmer to coalesce these docs into a single repo if we decide that is a good idea?

Michael.

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[Alex Bradbury]

On 26 October 2017 at 12:05, Michael Clark <michae...@mac.com> wrote:
> Hi Po-wei,
>
> The intention is that the content on the rv8 asm page will be merged with riscv-asm-manual. The goal of the rv8 page was to experiment with GitHub pages presentation as GitHub pages is not enabled on the riscv-asm-manual repo. I’ll add it to my todo list to make a pull request to sync these docs.
>
> I also noticed Alex recently mentioned his work on documenting compiler flags and there is the pre-existing work on documenting the ABI (calling convention and ELF relocations), all in different repos with essentially one file.
>
> There is also an ISA reference on the rv8 page, which is not intended to supplant the specification, rather the goal was to show the assembly language syntax as this is relevant for the assembly guide as the assembly language form of the instructions is currently missing from the specification. There are also many gaps in the currently assembly language docs as we jump straight into assembly language but we don’t show assembler and linker invocations.
>
> Some thought has to be put into the overall structure of the docs. We could also document linker scripts and how to achieve various linkage scenarios with newlib, libgloss and libnosys plus there are Liviu’s docs on RISC-V compiler defines that are also relevant to both GCC and LLVM. The compiler defines could potentially go in the compiler docs along with the flags.
>
> Given there are various and sundry docs, one wonders if we should instead have a single github.com/riscv/riscv-docs repo given most of these existing repos have a single file? e.g.
>
> - psabi.md
> - assembler.md
> - compiler.md
> - isa.md

I think there is value for the psabi doc being in a separate repo, if
only due to GitHub's limitations in subscribing to issues. There's
probably a different audience who want to get an email for every issue
or PR on the ABI than for user-facing documentation on assembler
mnemonics or the work I started on documenting/standardising toolchain
arguments+behaviours. Quite possible the non-psabi docs could be
easily merged to the same repo without triggering that concern.

> There is also the issue of presentation and the final form for these docs i.e. Markdown/reStructuredText/LaTeX. The last time we discussed this, the idea was to use Markdown for information collection and that the documentation may end up in a different form for presentation as the default rendering by GitHub for Markdown content is less than ideal. We could use restructured text or possibly even LaTeX or both…
>
> LLVM uses Sphinx which I believe is restructured text. I would be keen to try out Sphinx at some point as it can also be used to build PDF docs:
>
> - http://llvm.org/docs/

I think ultimately reST or Asciidoc are slightly less accessible for
writers, but tend to have better support for advanced features. We're
probably best getting the content right first and then think about
improving the presentation.

Best,

Alex

[uma graman]

Hello Michael,

     I am newbie in ASM and RISC-V. I am reading your material and writing some examples. I copied one of your sample/simple programs from the 1st list below. But I always get segmentation fault "User fetch segfault @ 0x0000000000000000." irrespective of the ASM program. Can you please help ? 

Thanks

Uma

[Bruce Hoult]

You should show the exact source code and commands you are using, and what hardware or emulator you are trying to run it on.

Although the code in the .o file will start at 0 in the text segment, on many platforms you can't execute code from address zero and the linker will put it somewhere else e.g. at 0x20400000 on the HiFIve1.

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